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http://dx.doi.org/10.6109/jkiice.2010.14.8.1887

Development of Switched-Capacitor Sigma-Delta Modulator for Automotive Radars  

Ryu, Jee-Youl (부경대학교 정보통신공학과)
Noh, Seok-Ho (안동대학교 전자공학과)
Abstract
This paper proposes a new switched-capacitor sigma-delta modulator for automotive radars. Developed modulator is used to perform high-resolution analog-to-digital conversion (ADC) of high frequency band signal in a radar system. It has supply voltage of 2.7V, and has body-effect compensated switch configuration with low voltage and low distortion. The modulator has been implemented in a $0.25{\mu}m$ double-poly and triple-metal standard CMOS process, and it has die area of $1.9{\times}1.5mm^{2}$. It showed better total harmonic distortion of 20dB than the conventional bootstrapped circuit at the supply voltage of 2.7V.
Keywords
Automotive radars; Sigma-delta modulator; Body-effect compensated switch;
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1 Vipul Jain et. al., "A Single-Chip Dual-Band 22-to-29GHz/77-to-81GHz BiCMOS Transceiver for Automotive Radars," 2009 IEEE International Solid-State Circuits Conference, pp. 308-309, February 2009.
2 Stephane Pinel et. al., "A 90nm CMOS 60GHz Radio," 2008 IEEE International Solid-State Circuits Conference, pp. 130-131,601, February 2008.
3 Yoichi Kawano et. al., "A 77GHz Transceiver in 90nm CMOS," 2009 IEEE International Solid-State Circuits Conference, pp. 310-311, February 2009.
4 S. Rabii and B. A. Wooley, The Design of Low-Voltage, Low-Power Sigma-Delta Modulators. Boston: Kluwer Academic Publishers, 1999.
5 J. C. Candy, A Use of Double Integration in Sigma-Delta Modulation, IEEE Trans. on Communications, vol. 33, pp. 249-258, Mar. 1985.   DOI
6 D. B. Ribner, A Comparison of Modulator networks for High-Order Oversampled Analog-to-Digital Converters, IEEE Trans. on Circuits and Systems, vol. 38, pp. 145-159, Feb. 1991.   DOI   ScienceOn
7 B. E. Boser and B. A. Wooley, The Design of Sigma-Delta Modulation Analog-to- Digital Converters, IEEE J. of Solid-State Circuits, vol. sc-23, no. 4, pp. 1298-1308, Dec. 1988.
8 J.-Y. Ryu and S.-H. Noh, "Development of the New Third-Order Cascaded Sigma-Delta Modulator," Conference of the Korean Institute of Maritime Information & Communication Science, Vol. 10, No. 2, pp. 835-838, October 2006.
9 S. Espejo et al, A 0.8-μm CMOS programmable Analog-Array-Processing Vision Chip with Local Logic and Image Memory, Proceedings of European Solid-State Cirucits Conference, pp. 280-283, 1996.
10 P. R. Gray, Analog ICs in the Submicron Era: Trends and Perspectives, Proceedings of IEEE Electron Devices Meeting, pp. 5-9, 1987.