• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.10
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• pp.1061-1070
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• 2009

In this paper, we have designed TDL(True-time Delay Line) for eliminating beam-squint occurring in active phased array antenna with large electrical size operated in wide bandwidth, and have tested its electrical performance. The proposed TDL device is composed of 4-bit microstrip delay line structure and MMIC amplifier for compensation of the delay-line loss. The measured results of gain and phase versus delay state satisfy the electrical requirements, also P1dB output power and noise figure meet the requirement. To verify the performance of fabricated TDL, we have simulated the beam patterns of wide-band active phased array antenna using the measured results and have certified the beam pattern compensation performance. As a result of simulated beam pattern compensation with respect to the 675.8 mm size antenna which is operated in X-band, 800 MHz bandwidth, we have reduced the beam squint error of ${\pm}1^{\circ}$ with ${\pm}0.1^{\circ}$. So this TDL module is able to be applied to active phase array antenna system.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.1
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• pp.1-6
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• 2019

An extremely small size multi-loop phase-locked loop(PLL) keeping phase noise performances has been proposed. It has been designed to have the loop filter made of small single capacitor with multiple Frequency Voltage Converters (FVCs) because the main goal is to make the size of the proposed PLL extremely small. Multiple FVCs which are connected to voltage controlled oscillator(VCO) make multiple negative feedback loops in PLL. Those multiple negative feedback loops enable the PLL with the loop filter made of an extremely small size single capacitor operate stably. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the 1.6ps jitter and $10{\mu}s$ locking time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.5
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• pp.971-980
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• 1994

The need increased capacity in the cellular system has resulted in the adoption of digital technology with CDMA as the channel access method. It has been recognized that the distinction of the base station is important for its performance in CDMA, since the same spreading sequences are used by the all base stations. Time offset of the pseudo-random noise binary code are used to distinguish signals received at a mobile station from different base station. But the start of the zero offset PN sequence is chosen arbitrary without the background of the systematic and mathematical elaboration. This paper proposes a mothed that define the start of the zero offset PN sequence mathematically. This paper also discusses a method that can easily calculate the time offset of the received spreading sequence with respect to the zero offset PN sequence.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.2
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• pp.207-217
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• 1993

In this paper, knowing a priori probability of phase offset between transmitted codes and reference codes in the receiver, we construct the state diagram of acquisition process of the direct sequence spread-spectrum communication system using the expanding window search. The scannings are performed from the cell with higher probability code epoch synchronization to that with lower one. We expand window size from initial value by r times of its previous size in each search, construct the corresponding the state diagrams, and derive average synchronization time using the Markov process and Mason's gain formula. Average synchronization times versus number of search n and detection probability $P_d$ are calculated.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.612-615
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• 2006

본 논문에서는 Late 암으로부터 측정된 상관 값을 보정하여 상관함수의 비대칭을 완화시키고 다중경로 신호 오차를 제거하는 새로운 상관기 설계법을 제안하였다. 다중경로 오차에 의한 신호 추적 오차는 상관함수의 Early-Late 간 비대칭과 관련이 있으므로, 다중상관기 구조를 이용하여 상관함수의 Early-Late간 상관값 차를 측정하면 상관함수의 비대칭 정도를 추정할 수 있다. 상관값 차를 이용하여 추정한 상관함수 비대칭을 감소시키면 다중경로 신호에 의한 코드 추적 오차를 줄일 수 있다. 제안한 상관기는 4개의 암과 보정치 생성 블록으로 구성된다. 제안한 상관기의 다중경로 오차 제거 성능은 시뮬레이션을 이용하여 확인하였다. 여러 가지 지연시간 및 신호 진폭을 가지는 다중경로 신호에 대하여 일반 수신기와의 위상 추적 오차를 비교하여 성능을 평가하였다. 시뮬레이션 결과에서 제안한 상관기는 우수한 다중경로 오차 제거 성능을 가지며 일반상관기와 유사한 평균 신호 획득시간을 가짐을 알 수 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.7-13
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• 2011

This paper presents a Time-to-Digital Converter which is a key block of an All-Digital Phase Locked Loop. In this work, a Vernier Delay Line is added in a conventional Gated Ring Oscillator, so it could get multi-phases and a high resolution. The Gated Ring Oscillator uses 7 unit delay cell, the Vernier Delay Line is used each delay cell. So proposed Time-to-Digital Converter uses total 21 phases. This Time-to-Digital Converter circuit is designed and laid out in $0.13{\mu}m$ 1P-6M CMOS technology. The proposed Time-to-Digital Converter achieves 26ps resolution, maximum input signal frequency is 100MHz and the digital output of proposed Time-to-Digital Converter are 8-bits. The proposed TDC detect 5ns phase difference between Start and Stop signal. A power consumption is 8.4~12.7mW depending on Enable signal width.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.24-32
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• 2017

In this paper, a low power 4th order delta-sigma modulator was designed with a high resolution of 12 bits or more for the biological signal processing. Using time-interleaving technique, 4th order delta-sigma modulator was designed with one operational amplifier. So power consumption can be reduced to 1/4 than a conventional structure. To operate stably in the big difference between the two capacitor for kT/C noise and chip size, the variable-stage amplifier was designed. In the first phase and second phase, the operational amplifier is operating in a 2-stage. In the third and fourth phase, the operational amplifier is operating in a 1-stage. This was significantly improved the stability of the modulator because the phase margin exists within 60~90deg. The proposed delta-sigma modulator is designed in a standard $0.18{\mu}m$ CMOS n-well 1 poly 6 Metal technology and dissipates the power of $354{\mu}W$ with supply voltage of 1.8V. The ENOB of 11.8bit and SNDR of 72.8dB at 250Hz input frequency and 256kHz sampling frequency. From measurement results FOM1 is calculated to 49.6pJ/step and FOM2 is calculated to 154.5dB.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.3
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• pp.15-24
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• 2022

At present, there are few studies on signal control of pedestrian traffic flow and non-motor traffic flow at intersections. Research on the optimization scheme of mixed traffic flow signal control can coordinate and control the overall traffic flow of pedestrians, non-motor vehicles and motor vehicles, which is of great significance to improve the congestion at intersections. For the traffic optimization of intersections, this paper starts from two aspects: channelization optimization and phase design, and reduces the number of conflict points at intersections from spatial and temporal right-of-way allocation respectively. Taking the classical signal timing method as the theoretical basis, and aiming at ensuring the safety and time benefit of traffic travelers, a channelization optimization and signal control scheme of the intersection is proposed. The channelization and phase design methods of intersections with motor vehicles, non-motor vehicles and pedestrians as objects are discussed, and measures to improve the channelization optimization of intersections are proposed. A multi-objective optimization model of intersection signal control was established, and the model was solved based on NSGA-II algorithm.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.8
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• pp.883-890
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• 2015

As the semiconductor processing technology has been developing, multiple cores or NoC(network on chip) can be contained in recent chips. GALS(globally asychronous locally synchronous) clocking scheme that has multi-clock domains with different frequencies or phase differences is widely used to solve power consumption and clock skew in a large chip with a single clock. A synchronizer is needed to avoid a synchronization problem between sender and receiver in GALS. In this paper, the setup and hold time of DFF required to design the synchronizer are measured using 180nm CMOS processing parameters depending on temperature, supply voltage, and the size of inverter in DFF. The simulation results based on the bisection method in HSPICE show that the setup and hold time are proportional to temperature, however they are inversely proportional to supply voltage, and negative values are measured for the hold time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.5
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• pp.1103-1108
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• 2010

In this paper, Frequency Synthesizer which is widely used for FH-SS system is proposed and the experimental results are analyzed. The performance of the DPLL(Digital Phase-Locked-Loop), which is the main part of the Synthesizer is analyzed by the computer program. Using Maxplus-II tool provided by altera. co., ltd, each part of the DPLL is designed and all of them is integrated into EPM7064SLC44-10 chip. And the simulation results are compared with the characteristics of the implemented circuits for analysis. And the experiential results show that the N value of the loop filter is toggled to adjacent N value, which result in phase jitter of the output. It can be resolved by increasing DCO(Digital Controlled oscillator) clock rate.