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http://dx.doi.org/10.6109/jkiice.2010.14.5.1103

Design and Performance Analysis of the Digital Phase-Locked Loop For Frequency Hopping Spread Spectrum system  

Kim, Seong-Cheol (우송대학교 방송통신시스템학과)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.14, no.5, 2010 , pp. 1103-1108 More about this Journal
Abstract
In this paper, Frequency Synthesizer which is widely used for FH-SS system is proposed and the experimental results are analyzed. The performance of the DPLL(Digital Phase-Locked-Loop), which is the main part of the Synthesizer is analyzed by the computer program. Using Maxplus-II tool provided by altera. co., ltd, each part of the DPLL is designed and all of them is integrated into EPM7064SLC44-10 chip. And the simulation results are compared with the characteristics of the implemented circuits for analysis. And the experiential results show that the N value of the loop filter is toggled to adjacent N value, which result in phase jitter of the output. It can be resolved by increasing DCO(Digital Controlled oscillator) clock rate.
Keywords
WLAN; Bluetooth; code acquisition; matched filter; frequency settling time; ISM;
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