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Design of a 26ps, 8bit Gated-Ring Oscillator Time-to-Digital Converter using Vernier Delay Line  

Jin, Hyun-Bae (School of Electronics Eng., INHA University)
Park, Hyung-Min (School of Electronics Eng., INHA University)
Kim, Tae-Ho (School of Electronics Eng., INHA University)
Kang, Jin-Ku (School of Electronics Eng., INHA University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.48, no.2, 2011 , pp. 7-13 More about this Journal
Abstract
This paper presents a Time-to-Digital Converter which is a key block of an All-Digital Phase Locked Loop. In this work, a Vernier Delay Line is added in a conventional Gated Ring Oscillator, so it could get multi-phases and a high resolution. The Gated Ring Oscillator uses 7 unit delay cell, the Vernier Delay Line is used each delay cell. So proposed Time-to-Digital Converter uses total 21 phases. This Time-to-Digital Converter circuit is designed and laid out in $0.13{\mu}m$ 1P-6M CMOS technology. The proposed Time-to-Digital Converter achieves 26ps resolution, maximum input signal frequency is 100MHz and the digital output of proposed Time-to-Digital Converter are 8-bits. The proposed TDC detect 5ns phase difference between Start and Stop signal. A power consumption is 8.4~12.7mW depending on Enable signal width.
Keywords
Time-to-Digital Converter(TDC); Gated Ring Oscillator(GRO); Vernier Delay Line(VDL); 1st-Order Noise Shaping;
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1 B. M. Helal, M. Z. Straayer, G. Y. Wei and M. H. Perrott, "A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance," IEEE Journal of Solid-State Circuits, vol. 43, no. 4, pp. 855-863, Apr. 2008.   DOI
2 R. B. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, and P. T. Balsara, "1.3V 20 ps Time-to-Digital Converter for Frequency Synthesis in 90-nm CMOS," IEEE Trans. Circuits Syst. II, Expr. Briefs, vol. 53, no. 3, pp. 220-224, Mar. 2006.   DOI
3 T.E. Rahkonen and J. T. Kostamovaara, "The use of stabilized CMOS Delay Lines for the Digitization of Short Time Intervals," IEEE J. Solid-State Circuits, vol. 28, no. 8, pp. 887-894, Aug. 1993.   DOI   ScienceOn
4 P. Chen, S. I. Liu, and J. Wu, "A CMOS Pulse-shrinking Delay Element for Time Interval Measurement," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 9, pp. 954-958, Sep. 2000.   DOI   ScienceOn
5 M.J. Lee, and A. Abidi, "A 9b, 1.25ps Resolution Coarse-Fine Time-to-Digital Converter in 90nm CMOS that Amplified a Time Residue," IEEE Journal of Solid-State Circuits, vol. 43, no. 4, pp. 769-777, Apr. 2008.
6 M. Z. Straayer and M. H. Perrott, "A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping," IEEE Journal of Solid-State Circuits, vol. 44, no. 4, pp. 1089-1098, Apr. 2009   DOI
7 J. Rogers, C. Plett, F. Dai, "Integrated Circuit Design for High-Speed Frequency Synthesis," Artech House. 2007.
8 Hwang Kyu-dong, "An Area Efficient Asynchronous Gated-Ring Oscillator Time-to- Digital Converter," M.S, Electric Engneering, KAIST, Feb. 2009.
9 Ramakrishnan V. and Balsara P.T., "A Wide-Range, High-Resolution, Compact, CMOS Time-to-Digital Converter," VLSI Design 2006, pp. 6, Jan. 2006.
10 Li G.H., and Chou H.P., "A High Resolution Time-to-Digital Converter using Two-level Vernier Delay Line Technique," Nuclear Science Symposium Conference Record, 2007. IEEE, vol. 1, pp. 276-280, Oct. 2007.