• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.155-161
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• 2018

A Si chip with the Cu/Au bumps of $100-{\mu}m$ diameter was flip-chip bonded using different anisotropic conductive adhesives (ACAs) onto the local stiffness-variant stretchable substrate consisting of polydimethylsiloxane (PDMS) and flexible printed circuit board (FPCB). The average contact resistances of the flip-chip joints processed with ACAs containing different conductive particles were evaluated and compared. The specimen, which was flip-chip bonded using the ACA with Au-coated polymer balls as conductive particles, exhibited a contact resistance of $43.2m{\Omega}$. The contact resistance of the Si chip, which was flip-chip processed with the ACA containing SnBi solder particles, was measured as $36.2m{\Omega}$, On the contrary, an electric open occurred for the sample bonded using the ACA with Ni particles, which was attributed to the formation of flip-chip joints without any entrapped Ni particles because of the least amount of Ni particles in the ACA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.4A
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• pp.408-416
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• 2010

A dumbbell-type CPW transmission-line structure has been proposed to improve the return loss of the transmission line between a driver IC and flip-chip-bonding VCSEL(Vertical Cavity Surface Emitting Laser) in a hybrid opto-electric circuit board(OECB). The proposed structure used a pair of dummy ground solder balls on the ground lines for flip-chip bonding of the VCSEL and designed the dumbbell-type CPW transmission line to improve reflection characteristics. The simulated results revealed that the return loss of the dumbbell-type CPW transmission line was 13-dB lower than the conventional CPW transmission line. A 4-dB improvement in the return loss was obtained using the dummy ground solder balls on the ground lines. The variation rate of the reflection characteristic with the variation of terminal impedances of the transmission line (at the output terminal of the driver IC and the input terminal of the VCSEL) is about ${\pm}2.5\;dB$.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.3
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• pp.1-6
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• 2014

The demand for fine-pitch devices is increasing due to an increase in I/O pin count, a reduction in power consumption, and a miniaturization of chip and package. In addition non-scalability of Cu pillar/Sn cap or Pb-free solder structure for fine-pitch interconnection leads to the development of bumpless interconnection system. Few bumpless interconnect systems such as BBUL technology, SAB technology, SAM technology, Cu-toCu thermocompression technology, and WOW's bumpless technology using an adhesive have been reviewed in this paper: The key requirements for Cu bumpless technology are the planarization, contamination-free surface, and surface activation.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.4
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• pp.8-16
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• 2023

The importance of next-generation packaging technologies is being emphasized as a solution as the miniaturization of devices reaches its limits. To address the bottleneck issue, there is an increasing need for 2.5D and 3D interconnect pitches. This aims to minimize signal delays while meeting requirements such as small size, low power consumption, and a high number of I/Os. Hybrid bonding technology is gaining attention as an alternative to conventional solder bumps due to their limitations such as miniaturization constraints and reliability issues in high-temperature processes. Recently, there has been active research conducted on SiCN to address and enhance the limitations of the Cu/SiO₂ structure. This paper introduces the advantages of Cu/SiCN over the Cu/SiO₂ structure, taking into account various deposition conditions including precursor, deposition temperature, and substrate temperature. Additionally, it provides insights into the core mechanisms of SiCN, such as the role of Dangling bonds and OH groups, and the effects of plasma surface treatment, which explain the differences from SiO₂. Through this discussion, we aim to ultimately present the achievable advantages of applying the Cu/SiCN hybrid bonding structure.

• Journal of the Korean institute of surface engineering
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• v.28 no.2
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• pp.67-76
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• 1995

The microstructure of 95wt.%Pb/5wt.%Sn and 63wt.%Sn/37wt.%Pb solders for flip chip bonding process has been characterized. Solders were deposited by thermal evaporation and reflowed in the conventional furnace or by rapid thermal annealing(RTA) process. As-deposited films show columnar structure. The microstructure of furnace cooled 63Sn/37Pb solder shows typical lamellar form, but that of RTA treated solder has the structure showing an uniform dispersion of Pb-rich phase in Sn matrix. The grain size of 95Pb/5Sn solder reflowed in the furnace is about $5\mu\textrm{m}$, but the grain size of RTA treated solder is too small to be observed. The microstructure in 63Sn/37Pb solder bump shows the segregation of Pb phase in the Sn rich matrix regardless of reflowing method. The 63Sn/37Pb solder bump formed by RTA process shows more uniform microstructure. These result are related to the heat dissipation in the solder bump.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.76-81
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• 2011

A new via cutting structure in 2-layer DRAM package substrate has been fabricated to lower its power distribution network(PDN) impedance. In new structure, part of the via is cut off vertically and its remaining part is designed to connect directly with the bonding pad on the package substrate. These via structure and substrate design not only provide high routing density but also improve the PDN impedance by shortening effectively the path from bonding pad to VSSQ plane. An additional process is not necessary to fabricate the via cutting structure because its structure is completed at the same time during a process of window area formation. Also, burr occurrence is minimized by filling the via-hole inside with a solder resist. 3-dimensional electromagnetic field simulation and S-parameter measurement are carried out in order to validate the effects of via cutting structure and VDDQ/VSSQ placement on the PDN impedance. New DRAM package substrate has a superior PDN impedance with a wide frequency range. This result shows that via cutting structure and power/ground placement are effective in reducing the PDN impedance.

• Proceedings of the KWS Conference
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• 2010.05a
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• pp.78-78
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• 2010

모바일 정보통신기기를 중심으로 패키지의 초소형화, 고집적화를 위해 플립칩 공법의 적용이 증가되고 있고 있으며 접속피치의 미세화에 따라 솔더 및 언더필을 사용하는 C4 공법보다 ACA(Anisotropic Conductive Adhesive), NCA (Non-conductive Adhesive) 등의 접착제를 이용하는 칩본딩 공법에 대한 요구가 증가하고 있다. 특히, NCA 공법의 경우 산업 현장의 대량생산에 대응하기 위해서는 접착제의 속경화 특성이 요구되어 진다. 일반적으로 접착제의 경화거동은 DSC(Differential Scanning Calorimeter)를 사용해 확인하지만, 수초 이내에 경화되는 접착제의 경우는 적용되기 어렵다. 본 연구에서는 이러한 전자패키지용 접착제의 속경화 거동을 효과적으로 평가할 수 있는 방법을 조사 하였다. 실험에서 사용된 접착제는 에폭시계 레진 기반에 이미다졸계 경화제를 사용한 기본적인 포뮬레이션을 사용하였고, 경화시간은 160^{\circ}C에서 1분 이내에 경화되는 특성을 가지고 있다. 경화 거동을 확인하기 위해서 isothermal DSC와 DEA(Dielectric Analysis)의 두가지 방법을 사용해 비교하였다. 두 실험 방법 모두 $160^{\circ}C$를 유지하며 경화 거동을 확인하였고, DoC(Degree of Cure)의 측정오차를 비교 분석하였다. DEA는 이온 모빌리티 변화에 따른 유전손실율을 측정하는 방법으로 80~90% 이후의 경화도는 측정되지 않았지만, 수초 이내에 경화되는 속경화 특성을 평가하기에 적합한 것으로 확인되었다.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.63-69
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• 2013

The warpage of a bottom package of Package on Package(PoP) where a chip was mounted to a substrate by flip chip process was compared to that of a bottom package for which a chip was bonded to a substrate using die attach film(DAF). At the solder reflow temperature of $260^{\circ}C$, the packages processed with flip chip bonding and DAF bonding exhibited warpages of $57{\mu}m$ and $-102{\mu}m$, respectively. At the temperature range between room temperature and $260^{\circ}C$, the packages processed with flip chip bonding and DAF bonding exhibited warpage values ranging from $-27{\mu}m$ to $60{\mu}m$ and from $-50{\mu}m$ to $-15{\mu}m$, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.11-15
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• 2010

In this paper, we focused on the optimization of bonding conditions for the successful thermo-compression bonding of electrodes between the RPCB and FPCB with Sn-Pb solder. The peel strength was proportionally affected by the bonding conditions, such as pressure, temperature, and time. In order to figure out an optimized bonding condition, fracture energies were calculated through F-x (force-displacement) curves in the peel test. The optimum condition for the thermo-compression bonding of electrodes between the RPCB and FPCB was found to be temperature of $225^{\circ}C$ and time of 7 s, and its peel strength was 22 N/cm.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.103-105
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• 2003

COG (Chip on Glass) technology using solder bump reflow has been investigated to attach IC chip directly on glass substrate of LCD panel. As It chip and LCD panel have to be heated to reflow temperature of the so]der bumps for COG bonding, it is necessary to use low-temperature solders to prevent the damage of liquid crystals of LCD panel. In this study, using the Sn-52In solder bumps of $40{\mu}m$ pitch size, solder joints between Si chip and glass substrate were made at temperature below $150^{\circ}C$. The contact resistance of the solder joint was $8.58m\Omega$, which was much lower than that of the joint made using the conventional ACF bonding technique. The Sn-52In solder joints with underfill showed excellent reliability at a hot humid environment.