| 1 |
C. S. Tan, D. F. Lim, S. G. Singh, S. K. Goulet, and M. Bergkvist, "Cu-Cu diffusion bonding enhancement at low temperature by surface passivation using self-assembled monolayer of alkanethiol", Appl. Phys. Lett., 95(19), 2108 (2009).
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| 2 |
C. Tan, L. Peng, J. Fan, Y. H. Li, and S. Gao, "Three-Dimensional Wafer Stacking Using Cu-Cu Bonding for Simultaneous Formation of Electrical, Mechanical, and Hermetic Bonds", IEEE Trans. Device Mater. 12, 194 (2012).
DOI
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| 3 |
D. F. Lim, X. F. Ang, J. Wei, C. M. Ng, C. S. Tan, "Void density reduction at the Cu-to-Cu bonding interface by means of prebonding surface passivation with self-assembled monolayer", ECSSSL, 13(12), H412 (2010).
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| 4 |
L. Peng, H. Y. Li, D. F. Lim, S. Gao, and C. S. Tan, "High density 3D interconnect of Cu-Cu contacts with enhanced contact resistance by self-assembled monolayer (SAM) passivation", IEEE Trans. Electron Devices, 58(8), 2500-2506 (2011).
DOI
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| 5 |
L. Peng, L. Zhang, H. Yi, G. Lo, and C. Tan, "Mechanical characterization of wafer level bump-less Cu-Cu bonding", IEEE EPTC, 437 (2012).
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| 6 |
P. Enquist, G. Fountain, C. Petteway, A. Hollingsworth, H., "Low Cost of Ownership scalable copper Direct Bond Interconnect 3D IC technology for three dimensional integrated circuit applications", IEEE 3D System Integration, 1-6 (2009).
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| 7 |
C. S. Tan, D. F. Lim, X. F. Ang, J. Wei, and K. C. Leong, "Low temperature Cu-Cu thermo-compression bonding with temporary passivation of self-assembled monolayer and its bond strength enhancement", Microelectronics Reliab., 52, 321 (2012).
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| 8 |
P. R. Morrow, C. M. Park, S. Ramanathan, M. J. Kobrinsky, and M. Harmes, "Three-Dimensional Wafer Stacking Via Cu- Cu Bonding Integrated With 65-nm Strained-Si/Low-k CMOS Technology", IEEE Electron Device Letters, 27(5), 335 (2006).
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| 9 |
J. Lau, "Resent advances and new trend in nanotechnology and 3D integration for semiconductor industry", ESC Transactions, 44(1), 805 (2012).
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| 10 |
D. Diehl, H. Kitada, N. Maeda, K. Fujimoto, S. Ramaswami, K. Sirajuddin, R. Yalamanchili, B. Eaton, N. Rajagopalan, R. Ding, S. Patel, Z. Cao, M. Gage, Y. Wang, W. Tu, S.W. Kim, R. Kulzer, I. Drucker, D. Erickson, T. Ritzdorf, T. Nakamura, T. Ohba, "Formation of TSV for the stacking of advanced logic devices utilizing bumpless wafer-on-wafer technology", Microelectron. Eng., 92, 3 (2012).
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ScienceOn
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| 11 |
N. Maeda, H. Kitada, K. Fujimoto, Y. S. Kim, S. Kodama, S. Yoshimi, M. Akazawa, Y. Mizushima, and T. Ohba, "Development of Ultra Thin Chip-on-Wafer Process using Bumpless Interconnects for Three Dimensional Memory/ Logic Applications", IEEE VLSI Tech., 171 (2012).
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| 12 |
T. Ohba, "Wafer level three-dimensional integration (3D) using bumpless TVSV interconnects for tera-scale generation, IEEE ISCDG, 1-4 (2013).
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| 13 |
P. Enquist, "High density bond interconnect (DBI) technology for three dimenssional integrated circuit applications", Mater. Res. Sco. Sump. Proc. 970 (2007) .
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| 14 |
T. Ohba, "Bumpless through-dielectrics-silicon via technology for wafer based three-dimensional integration", ECS Transactions, 44(1), 827 (2012).
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| 15 |
C. S. Tam, L. Peng, H. Y. Li, D. F. Lin, and S. Gao, "Waferon- wafer stacking by bumpless Cu-Cu bonding and its electrical characteristics", IEEE EDL, 32(7), 943 (2011).
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| 16 |
H. Braunisch, S. Towle, R. Emery, C. Hu, and G. Vandentop, "Electrical Performance of Bumpless Build-up Layer Packaging", IEEE ECTC, 353 (2002).
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| 17 |
A. Shigetou, T. Itoh, K. Sawada, and T. Suga, "Bumpless Interconnect of 6- m pitch Cu Electrodes at Room Temperature", IEEE ECTC, 1405 (2008).
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| 18 |
Shigetou, T. Itoh, M. Matsuo, N. Hayasaka, K. Okumura, and T. Suga, "Bumpless Interconnect Through Ultrafine Cu Electrodes by Means of Surface-Activated Bonding (SAB) Method", IEEE Trans. Adv. Packag., 29(2), 218 (2006).
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| 19 |
C. Lin, S. Chiang, and T. K. Yang, "Bumpless Flip Chip Packages", Int. Symp. Elcct. Mater. Packag., 173 (2002).
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| 20 |
L. Cadix, "Flip-Chip Market and Technology Trend", Yole Development (2013).
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| 21 |
A. Shigetou, T. Itoh, and T. Suga, "Electrical Performance and Reliability of Fine-Pitch Cu Bumpless Interconnect", IEEE ECTC, 1114 (2005).
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| 22 |
S. Towle, H. Braunisch, C. Hu, R. Emery, and G. Vandentop, "Bumpless Build-up Layer Packaging", Proc. ASME, IMECE, EPP-24703 (2001).
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| 23 |
K. Saito, T. Fujii, Y. Akiyama, T. Usami, K. Otsuka, and T. Suga, "Study on the Electrical Performance of 80 m Pitch Bumpless Bonding for Several GHz Interconnection", IEEE ECTC 1127 (2005).
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| 24 |
T. H. Kim, M. M. R. Howlader, T. Itoh, T. Suga, "Room temperature Cu-Cu direct bonding using surface activated bonding method", J. Vac. Sci. Technol. A, 21(2), 449 (2003).
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| 25 |
W. Yang, M. Akaike, M. fujino, T. Suga, "A combined process of formic acid pretreatment for low-temperature bonding of copper electrodes", ECS SSST, 2(6), 271 (2013).
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| 26 |
M. Park, S. E. Kim, "Study of Ar plasma treatment on Cu interconnect surface for Cu bonding in 3D integration", Proc. of MRS-K Fall, 27 (2013).
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| 27 |
C. Lin, S. Chiang, and T. K. Yang, "3D Stackable Packages with Bumpless Interconnect Technology", IEEE EPTC, 8 (2003).
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| 28 |
T. Ohba, "Bumpless WOW Stacking for Large-Scale 3D Integration", IEEE ICSICT, 70-73 (2010).
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| 29 |
C. S. Tan, G. Y. Chong, "High throughput Cu-Cu bonding by non-thermo-compression method", IEEE ECTC, 1158 (2013).
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| 30 |
J. Kim, K. Kim, H. Lee, H. Kim, Y. Park, S. Hyun, "The effect of plasma pre-cleaning on the Cu-Cu direct bonding for 3D chip stacking", IEEE IPFA, 1-4 (2011).
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| 31 |
J. Cho, S. Yu, M. Roma, S. Maganty, S. Park, E. Bersch, C. Kim and B. Sapp, "Mechanism of low-temperature copper-tocopper direct bonding for 3D TSV package interconnection", TIEEE ECTC, 1133 (2013).
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| 32 |
J. Fan, D. F. Lim, and C. S. Tan, "Effects of surface treatment on the bonding quality of wafer-level Cu-to-Cu thermo-compression bonding for 3D integration", J. Micromech. Microeng., 23, 045025 (2013).
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