• Title/Summary/Keyword: 비아홀

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Study on Via hole formation in multi layer MCM-D substrate using photosensitive BCB (감광성 BCB를 사용한 다층 MCM-D 기판에서 비아홀 형성에 관한 연구)

  • 주철원;최효상;안용호;정동철;김정훈;한병성
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2000.07a
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    • pp.99-102
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    • 2000
  • Via for achieving reliable fabrication of MCM-D substrate was formed on the photosensitive BCB layer. MCM-D substrate consists of photosensitive BCB(Benzocyclobutene) interlayer dielectric and copper conductors. In order to form the vias in photosensitive BCB layer, the process of BCB and plasme etch using $C_2$F$_{6}$ gas were evaluated. The thickness of BCB after soft bake was shrunk down to 60% of the original. AES analysis was done on two vias, one is etched in $C_2$F$_{6}$ gas and the other is non etched. On via etched in $C_2$F$_{6}$, native C was detected and the amount of native C was reduced after Ar sputter. On via non etched in $C_2$F$_{6}$, organic C was detected and amount of organic C was reduced a little after Ar sputter. As a result of AES, BCB residue was not removed by Ar sputter, so plasma etch is necessary for achieving reliable via.ble via.

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ED COB Package Using Aluminum Anodization (알루미늄 양극산화를 사용한 LED COB 패키지)

  • Kim, Moonjung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.10
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    • pp.4757-4761
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    • 2012
  • LED chip on board(COB) package has been fabricated using aluminum substrate and aluminum anodization process. An alumina layer, used as a dielectric in COB substrate, is produced on aluminum substrate by selective anodization process. Also, selective anodization process makes it possible to construct a thermal via with a fully-filled via hole. Two types of the COB package are fabricated in order to analyze the effects of their substrate types on thermal resistivity and luminous efficiency. The aluminum substrate with the thermal via shows more improved measurement results compared with the alumina substrate. These results demonstrate that selective anodization process and thermal via can increase heat dissipation of COB package in this work. In addition, it is proved experimentally that these parameters also can be enhanced using efficient layout of multiple chip in the COB package.

Study on Self-Heating Effects in AlGaN/GaN-on-Si Power Transistors (AlGaN/GaN-on-Si 전력스위칭소자의 자체발열 현상에 관한 연구)

  • Kim, Shin Young;Cha, Ho-Young
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.2
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    • pp.91-97
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    • 2013
  • Self-heating effects during operation of high current AlGaN/GaN power transistors degrade the current-voltage characteristics. In particular, this problem becomes serious when a low thermal conductivity Si substrate is used. In this work, AlGaN/GaN-on-Si devices were fabricated with various channel widths and Si substrate thicknesses in which the structure dependent self-heating effects were investigated by temperature dependent measurements as well as thermal simulation. Accordingly, a device structure that can effectively dissipate the heat was proposed in order to achieve the maximum current in a multi-channel, large area device. Employing via-holes and common electrodes with a 100 ${\mu}m$ Si substrate thickness improved the current level by 75% reducing the channel temperature by 68%.

Design of Flexible Reconfigurable Frequency Selective Surface for X-Band Applications (유연한 구조를 갖는 X-Band 재구성 주파수 선택구조 설계)

  • Lee, In-Gon;Park, Chan-Sun;Yook, Jong-Gwan;Park, Yong-Bae;Chun, Heung-Jae;Kim, Yoon-Jae;Hong, Ic-Pyo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.28 no.1
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    • pp.80-83
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    • 2017
  • In this paper, the X-band reconfigurable frequency selective surface having flexible geometry was proposed. The proposed RFSS is composed of patterns of cross-shaped loop with inductive stub, which can control the frequency response for C-Band and X-band by ON/OFF state of PIN diode. To minimize the parasitic effect and to obtain the high level of isolation between the unit cell of FSS and the bias circuit, we designed the grid type bias line on bottom layer through via hole. The measured transmission characteristics show good agreement with the simulation results and good stability of frequency response for different incident angles and curvatures of surface.

Low Cost Via-Hole Filling Process Using Powder and Solder (파우더와 솔더를 이용한 저비용 비아홀 채움 공정)

  • Hong, Pyo-Hwan;Kong, Dae-Young;Nam, Jae-Woo;Lee, Jong-Hyun;Cho, Chan-Seob;Kim, Bonghwan
    • Journal of Sensor Science and Technology
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    • v.22 no.2
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    • pp.130-135
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    • 2013
  • This study proposed a noble process to fabricate TSV (Through Silicon Via) structure which has lower cost, shorter production time, and more simple fabrication process than plating method. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process. The via hole was $100{\mu}m$ in diameter and $400{\mu}m$ in depth. A dielectric layer of $SiO_2$ was formed by thermal oxidation on the front side wafer and via hole side wall. An adhesion layer of Ti and a seed layer of Au were deposited. Soldering process was applied to fill the via holes with solder paste and metal powder. When the solder paste was used as via hole metal line, sintering state and electrical properties were excellent. However, electrical connection was poor due to occurrence of many voids. In the case of metal powder, voids were reduced but sintering state and electrical properties were bad. We tried the via hole filling process by using mixing solder paste and metal powder. As a consequence, it was confirmed that mixing rate of solder paste (4) : metal powder (3) was excellent electrical characteristics.

Optimization of Laser Process Parameters for Realizing Optimal Via Holes for MEMS Devices (MEMS 소자의 비아 홀에 대한 레이저 공정변수의 최적화)

  • Park, Si-Beom;Lee, Chul-Jae;Kwon, Hui-June;Jun, Chan-Bong;Kang, Jung-Ho
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.34 no.11
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    • pp.1765-1771
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    • 2010
  • In the case of micro.electro-mechanical system (MEMS) devices, the quality of punched via hole is one of the most important factors governing the performance of the device. The common features that affect the laser micromachining of via holes drilled by using Nd:$YVO_4$ laser are described, and efficient optimization methods to measure them are presented. The analysis methods involving an orthogonal array, analysis of variance (ANOVA), and response surface optimization are employed to determine the main effects and to determine the optimal laser process parameters. The significant laser process parameters were identified and their effects on the quality of via holes were studied. Finally, an experiment in which the optimal levels of the laser process parameters were used was carried out to demonstrate the effectiveness of the optimization method.

Embedded Ferrite Film Inductor in PCB Substrate (PCB기판에 임베디드 된 페라이트 필름 인덕터)

  • Bae, Seok;Mano, Yasuiko
    • Journal of the Korean Magnetics Society
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    • v.15 no.1
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    • pp.30-36
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    • 2005
  • Recently, It has been reported that the spin sprayed ferite film shows better magnetic properties at high frequeny that the ferrite by co-firing over $800^{\circ}C$ . Besides, there is no limitation to select the substrate materials because it can be processed with relatively low temperature below $100^{\circ}C$. Therefore, we fabricated film inductor as a passive device for DC-DC converter by a use of spin sprayed embedded form was completed by via hole process of pad opening. Saturation magnetization of 0.61 T and real part of permeability of 110 were obtained in Ni-Zn ferrite. In addition, inductance of 1.52 ${\mu}H$, quality factor of 24.3 at 5 MHz were measured with spiral 16 turn inductor. The rated current of inductor was 863 mA.

Tri-Band Folded Monopole Antenna Design with MNG Single Cell Metamaterial Loading (MNG 단일셀 메타매질 부하를 갖는 삼중대역 폴디드 모노폴 안테나 설계)

  • Lee, Young-Hun
    • Journal of IKEEE
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    • v.22 no.1
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    • pp.127-135
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    • 2018
  • This paper was studied the tri-band folded monopole antenna design with Mu-negative metamaterial unit cell, which operates at 700 MHz UHD broadcast band and 2.45 GHz/5 GHz WiFi band. The MNR metamaterial is fabricated by forming a capacitor on the backside of the antenna substrate and connecting it to the ground plane through a strip line and a via hole so that a single cell can operate in the MZR (Mu zero resonator). Through this, the resonance point can be controlled to resonate in the zero mode in 700 MHz band, and the bandwidth is improved. Experimental results show that the 10dB bandwidth and gain are 309 MHz (41.2%) and 5.298 dB at the first resonance point, and the 10dB bandwidth and gain at the second resonance point are 821.9 MHz (33.5%) and 2.7840 dB respectively. At the third resonance point, the gain and bandwidth were 1.1314 GHz (20.6%) and 2.9484 dB respectively. We confirmed that the resonance point with theoretical value is in agreement with experimental value. And the radiation pattern is generally omnidirectional, and it has been confirmed that the radiation pattern is good in both forward and backward directions at 0.75 GHz and 2.45 GHz, and has a radiation pattern with multiple lobes at 5.5 GHz.

High-Speed Cu Filling into TSV and Non-PR Bumping for 3D Chip Packaging (3차원 실장용 TSV 고속 Cu 충전 및 Non-PR 범핑)

  • Hong, Sung-Chul;Kim, Won-Joong;Jung, Jae-Pil
    • Journal of the Microelectronics and Packaging Society
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    • v.18 no.4
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    • pp.49-53
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    • 2011
  • High-speed Cu filling into a through-silicon-via (TSV) and simplification of bumping process by electroplating for three dimensional stacking of Si dice were investigated. The TSV was prepared on a Si wafer by deep reactive ion etching, and $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to increase the filling rate of Cu into the via, a periodic-pulse-reverse wave current was applied to the Si chip during electroplating. In the bumping process, Sn-3.5Ag bumping was performed on the Cu plugs without lithography process. After electroplating, the cross sections of the vias and appearance of the bumps were observed by using a field emission scanning electron microscope. As a result, voids in the Cu-plugs were produced by via blocking around via opening and at the middle of the via when the vias were plated for 60 min at -9.66 $mA/cm^2$ and -7.71 $mA/cm^2$, respectively. The Cu plug with a void or a defect led to the production of imperfect Sn-Ag bump which was formed on the Cu-plug.

Cu Electroplating on the Si Wafer and Reliability Assessment of Low Alpha Solder Bump for 3-D Packaging (3차원 실장용 실리콘 웨이퍼 Cu 전해도금 및 로우알파솔더 범프의 신뢰성 평가)

  • Jung, Do Hyun;Lee, Joon Hyung;Jung, Jae Pil
    • Proceedings of the Korean Institute of Surface Engineering Conference
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    • 2012.11a
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    • pp.123-123
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    • 2012
  • 최근 연구되고 있는 TSV(Through Silicon Via) 기술은 Si 웨이퍼 상에 직접 전기적 연결 통로인 관통홀을 형성하는 방법으로 칩간 연결거리를 최소화 할 수 있으며, 부피의 감소, 연결부 단축에 따른 빠른 신호 전달을 가능하게 한다. 이러한 TSV 기술은 최근의 초경량화와 고집적화로 대표되는 전자제품의 요구를 만족시킬 수 있는 차세대 실장법으로 기대를 모으고 있다. 한편, 납땜 재료의 주 원료인 주석은 주로 반도체 소자의 제조, 반도체 칩과 기판의 접합 및 플립 칩 (Flip Chip) 제조시의 범프 형성 등 반도체용 배선재료에 널리 사용되고 있다. 최근에는 납의 유해성 때문에 대부분의 전자제품은 무연솔더를 이용하여 제조되고 있지만, 주석을 이용한 반도체 소자가 고밀도화, 고 용량화 및 미세피치(Fine Pitch)화 되고 있기 때문에, 반도체 칩의 근방에 배치된 주석으로부터 많은 알파 방사선이 방출되어 메모리 셀의 정보를 유실시키는 소프트 에러 (Soft Error)가 발생되는 위험이 많아지고 있다. 이로 인해, 반도체 소자 및 납땜 재료의 주 원료인 주석의 고순도화가 요구되고 있으며, 특히 알파 방사선의 방출이 낮은 로우알파솔더 (Low Alpha Solder)가 요구되고 있다. 이에 따라 본 연구는 4인치 실리콘 웨이퍼상에 직경 $60{\mu}m$, 깊이 $120{\mu}m$의 비아홀을 형성하고, 비아 홀 내에 기능 박막증착 및 전해도금을 이용하여 전도성 물질인 Cu를 충전한 후 직경 $80{\mu}m$의 로우알파 Sn-1.0Ag-0.5Cu 솔더를 접합 한 후, 접합부 신뢰성 평가를 수행을 위해 고속 전단시험을 실시하였다. 비아 홀 내 미세구조와 범프의 형상 및 전단시험 후 파괴모드의 분석은 FE-SEM (Field Emission Scanning Electron Microscope)을 이용하여 관찰하였다. 연구 결과 비아의 입구 막힘이나 보이드(Void)와 같은 결함 없이 Cu를 충전하였으며, 고속전단의 경우는 전단 속도가 증가할수록 취성파괴가 증가하는 경향을 보였다. 본 연구를 통하여 전해도금을 이용한 비아 홀 내 Cu의 고속 충전 및 로우알파 솔더 볼의 범프 형성이 가능하였으며, 이로 인한 전자제품의 소프트에러의 감소가 기대된다.

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