• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.11
• /
• pp.50-57
• /
• 2013

This paper provides a design of high-throughput parallel turbo decoder that is able to decode several packets of various length simultaneously. For high-speed communications, designing of Turbo decoder as parallel structures reduces the long decoding time caused by iterative turbo decode way. Also, by employing the double buffer structure for input and output packets improves the decoder throughput by enabling continuous decoding. Because parallel turbo decoder is designed to be able to decode the packet of the longest length, there exist idle PE's(Processing Element) in the case of decoding packets of short length. The main idea of this paper is to increase the utilization of PE's in parallel Turbo decoder and to improve the decoder throughput by using the idle PE's immediately for the subsequent packets decoding. For this, the control is necessary to enable the concurrent decoding of several short packets and we propose the method of this control. Applying the proposed method, we implemented Turbo Decoder with 32 PE's that can decode packets of 6144 bits maximum. Compared to the conventional Turbo decoder, although the area was increased about 16%, the decoder throughput was improved 28 times for short packets.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.48 no.7
• /
• pp.9-16
• /
• 2011

In this paper, various kinds of high throughput turbo decoding schemes are introduced, and a new turbo decoding scheme using the advantages of each scheme is proposed. The proposed scheme uses the decoding structure of double flow scheme, sliding window scheme and shuffled turbo decoding scheme. Simulation results show that the proposed scheme offers a BER performance equivalent to those of existing turbo decoding schemes with less clock cycles. We also show that the required memory can be reduced by choosing proper size of sliding window. Consequently, we can design a high throughput turbo decoder requiring low power and low area.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.9A
• /
• pp.924-933
• /
• 2008

This paper proposes a novel LDPC code decoder architecture to improve throughput for DVB-S2, a second generation standard of ETSI for satellite broad-band applications. The proposed architecture clusters 360 bitnodes and checknodes into groups utilizing the property of IRA-LDPC code. Functional modules which perform calculations for bitnode groups and checknode groups have local memories and store the messages from the other type of functional modules connected by edges at their local memories. The proposed architecture can avoid memory conflicts by accessing stored messages sequentially, hence, increases throughput in the proposed DVB-S2 LDPC code decoder architecture. The proposed architecture was synthesized using the TSMC 90nm technology. Synthesis results show that throughput of the proposed architecture is improved by 104% and 478%, respectively, when compared with those of the architectures proposed by F. Kienle and J. Dielissen.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.2
• /
• pp.104-113
• /
• 2013

A high-throughput Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder architecture is proposed for 60GHz multi-gigabit wireless personal area network (WPAN) applications. Two novel techniques which can apply to our selected QC-LDPC code are proposed, including a four block-parallel layered decoding technique and fixed wire network. Two-stage pipelining and four block-parallel layered decoding techniques are used to improve the clock speed and decoding throughput. Also, the fixed wire network is proposed to simplify the switch network. A 672-bit, rate-1/2 QC-LDPC decoder architecture has been designed and implemented using 90-nm CMOS standard cell technology. Synthesis results show that the proposed QC-LDPC decoder requires a 794K gate and can operate at 290 MHz to achieve a data throughput of 3.9 Gbps with a maximum of 12 iterations, which meet the requirement of 60 GHz WPAN applications.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.9
• /
• pp.2029-2035
• /
• 2013

In this paper, we presented non-uniform quantization method for LDPC decoder specified in DVB-S2 standard. There are some problems in order to implement LDPC decoder in aspect to algorithm and implementation. In algorithm aspect, because of large number of iterations, LDPC decoding in general give rise to a large number of computation operations, mass power consumption, and decoding delay. Therefore, this paper studies Horizontal Shuffle Scheduling (HSS) algorithm which reduced iteration number without performance loss. In aspect of implementation, there are some solutions to improve the decoding speed, however this paper focused on non-uniform quantization which reduce the quantization bits of LDPC decoder. In simulation results, Decoding throughput of HSS LDPC decoder based on non-uniform quantization is 816Mbps and it improved 12% compared to conventional one.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.35 no.3C
• /
• pp.287-294
• /
• 2010

MB-OFDM UWB system will adopt LDPC codes to enhance the decoding performance with higher data rates. In this paper, we will consider algorithm and architecture of the LDPC codes in MB-OFDM UWB system. To suggest the hardware efficient LDPC decoder architecture, LLR(log-likelihood-ration) calculation algorithms and check node update algorithms are analyzed. And we proposed the architecture of LDPC decoder for the high throughput application of Wimedia UWB. We estimated the feasibility of the proposed architecture by implementation in a FPGA. The implementation results show our architecture attains higher throughput than other result of QC-LDPC case. Using this architecture, we can implement LDPC decoder for high throughput transmission, but it is 0.2dB inferior to the BP algorithm.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.4
• /
• pp.48-58
• /
• 2016

This paper presents the high-throughput fully-parallel architecture for GF(64) (160,80) regular (2,4) non-binary LDPC (NB-LDPC) codes decoder based on the extended min sum algorithm. We exploit the NB-LDPC code that features a very low check node and variable node degree to reduce the complexity of decoder. This paper designs the fully-parallel architecture and allows the interleaving check node and variable node to increase the throughput of the decoder. We further improve the throughput by the proposed early sorting to reduce the latency of the check node operation. The proposed decoder has the latency of 37 cycles in the one decoding iteration and achieves a high throughput of 1402Mbps at 625MHz.

• Journal of IKEEE
• /
• v.24 no.2
• /
• pp.550-558
• /
• 2020

Successive cancellation (SC) decoding that is one of the decoding algorithms for polar codes has long decoding latency and low throughput because of the nature of successive decoding. To reduce the latency and increase the throughput, various decoding structures for polar codes are presented. In this paper, we compare the previous decoding structures and analyze them by dividing into two types, pruning and multi-path decoders. Decoders for applying pruning are representative of SSC (simplified SC), Fast-SSC and redundant-LLR structures, and decoders with multi-path are representative of 2-bit SC and redundant-LLR structures. All the previous structures are compared in terms decoding latency and hardware area, and according to the comparison, the syndrome check based decoder has the lowest latency and redundant-LLR decoder has the highest hardware efficiency.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.5 no.3
• /
• pp.164-168
• /
• 2012

LDPC decoder architectures are generally classified into serial, parallel and partially parallel architectures. Conventional method of LDPC decoding in general give rise to a large number of computation operations, mass power consumption, and decoding delay. It is necessary to reduce the iteration numbers and computation operations without performance degradation. This paper studies Horizontal Shuffle Scheduling (HSS) algorithm. In the result, number of iteration is half than conventional algorithm without performance degradation. Finally, this paper present design methodology of high-speed LDPC decoder and confirmed its throughput is up to about 600Mbps.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.49 no.4
• /
• pp.335-342
• /
• 2021

By using HLS when developing a communication system FPGA, HDL code can be automatically generated from a little modified C/C++ source code used for performance verification, which has the advantage of shortening the development period. In this paper, a method of designing a telemetry standard 106-17 LDPC decoder in C language is proposed using Xilinx's Vivado HLS, and by synthesizing Spartan-7 and Kintex-7 as target devices, throughput and FPGA utilization rate was compared.