전자공학회논문지 (Journal of the Institute of Electronics and Information Engineers)

  • 제53권4호
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  • Pages.48-58
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  • 2016
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  • 2287-5026(pISSN)
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  • 2288-159X(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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1.4 Gbps 비이진 LDPC 코드 복호기를 위한 Fully-Parallel 아키텍처

Fully-Parallel Architecture for 1.4 Gbps Non-Binary LDPC Codes Decoder

  • 최인준 (충남대학교 전자전파정보통신공학과) ;
  • 김지훈 (서울과학기술대학교 전기정보공학과)
  • Choi, Injun (Dept. of Electronics Engineering, Chungnam National University) ;
  • Kim, Ji-Hoon (Dept. of Electrical and Information Engineering, Seoul National University of Science and Technology)
  • 투고 : 2016.01.19
  • 심사 : 2016.04.06
  • 발행 : 2016.04.25
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초록

본 논문은 GF(64) (160,80) 정규 (2,4) 비이진 LDPC 코드 복호기를 위한 높은 처리량의 병렬 아키텍처를 제안한다. 복호기의 복잡도를 낮추기 위해 체크 노드와 변수 노드의 차수가 작은 코드를 사용하며 뛰어난 에러 정정 성능을 위해 높은 위수의 유한체에서 정의된 코드를 사용한다. 본 논문은 Fully-parallel 아키텍처를 설계하고 체크 노드와 변수 노드를 interleaving하여 복호기의 데이터 처리량을 향상시켰다. 또한 체크 노드의 초기화 지연을 단축시킬 수 있는 조기 분류 기법을 제안하여 데이터 처리량을 추가로 향상시켰다. 제안된 복호기는 1 iteration에 37사이클이 소요되며 625MHz 동작주파수에서 1402Mbps의 데이터 처리량을 갖는다.

This paper presents the high-throughput fully-parallel architecture for GF(64) (160,80) regular (2,4) non-binary LDPC (NB-LDPC) codes decoder based on the extended min sum algorithm. We exploit the NB-LDPC code that features a very low check node and variable node degree to reduce the complexity of decoder. This paper designs the fully-parallel architecture and allows the interleaving check node and variable node to increase the throughput of the decoder. We further improve the throughput by the proposed early sorting to reduce the latency of the check node operation. The proposed decoder has the latency of 37 cycles in the one decoding iteration and achieves a high throughput of 1402Mbps at 625MHz.

키워드

참고문헌

  1. T. J. Richardson, M. A. Shokrollahi, and R. L. Urbanke, "Design of capacity-approaching low-density parity check codes", IEEE Trans. Inf. Theory, vol. 47, pp. 619-637, Feb. 2001 https://doi.org/10.1109/18.910578
  2. M. C. Davey and D. MacKay, "Low-density parity check codes over GF(q)", IEEE Commun. Lett., vol. 2, no. 6, pp. 165-167, Jun. 1998. https://doi.org/10.1109/4234.681360
  3. L. Barnault and D. Declercq, "Fast decoding algorithm for LDPC over GF($q^2$)", in Proc. IEEE Inf. Theory Workshop, pp. 70-73, Mar. 2003
  4. H. Wymeersch, H. Steendam, and M. Moeneclaey, "Log-domain decoding of LDPC codes over GF(q)", in Proc. IEEE Int. Conf. Commun., vol. 2, pp. 772-776, Jun. 2004
  5. D. Declercq and M. Fossorier, "Decoding algorithms for nonbinary LDPC codes over GF(q)", IEEE Trans. Commun., vol. 55, no. 4, pp. 633-643, Apr. 2007. https://doi.org/10.1109/TCOMM.2007.894088
  6. V. Savin, "Min-max decoding for non binary LDPC codes", in Proc. IEEE Int. Symp. Inf. Theory, pp. 960-964, Jul. 2008
  7. X. Chen and C.-L. Wang, "High-throughput efficient non-binary LDPC decoder based on the simplified min-sum algorithm, IEEE Trans". Circuits Systems I: Regular Papers, vol. 59, no. 11, pp.2784 -2794, Nov. 2012 https://doi.org/10.1109/TCSI.2012.2190668
  8. E. Li, K. Gunnam, and D. Declercq, "Trellis based extended min-sum for decoding nonbinary LDPC codes", in Proc. 8th Int. Symp. Wireless Commun. Syst. (ISWCS, pp. 46-50), Nov. 2011
  9. C. Poulliat, M. Fossorier and D. Declercq, "Design of regular (2,$d_c$)-LDPC codes over GF(q) using their binary images", vol. 56, no. 10, pp.1626-1635, Oct. 2008 https://doi.org/10.1109/TCOMM.2008.060527
  10. A. Venkiah, D. Declercq and C. Poulliat, "Design of Cages with a Randomized Progressive Edge-Growth Algorithm", in IEEE Commun. Letters, vol. 12, pp. 1-3, Apr. 2008. https://doi.org/10.1109/LCOMM.2008.071450
  11. A. Voicila, D. Declercq, F. Verdier, M. Fossorier and P. Urard, "Low-complexity decoding for non-binary LDPC codes in high order fields", IEEE Trans. Commun., vol. 58, no. 5, pp. 1365-1375 May 2010 https://doi.org/10.1109/TCOMM.2010.05.070096
  12. E. Boutillon and L. Conde-Canencia, "Bubble check: A simplified algorithm for elementary check node processing in extended min-sum non-binary LDPC decoders", IEEE Electron. Lett., vol. 46, no. 9, pp.633-634, Apr. 2010. https://doi.org/10.1049/el.2010.0566
  13. Y. Jung, Y. Jung, S. Lee, and J. Kim, "8.1 Gbps High-Throughput and Multi-Mode QC-LDPC Decoder based on Fully Parallel Structure", Journal of The Institute of Electronics Engineers of Korea, vol. 50, no. 10, pp. 78-89, Oct. 2013
  14. J. Park, S. Lee, K. Chung, S. Cho, J. Ha, and Y. Song, "A Memory-efficient Partially Parallel LDPC Decoder for CMMB Standard", The Institute of Electronics Engineers of Korea - Semiconductor and Devices vol. 48, no. 1, pp. 22-30, jan. 2011
  15. Y. S. Park, Y. Tao and Z. Zhang, "A fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating", IEEE J. Solid-State Circuits, vol. 50, no. 2, pp.464-475, Feb. 2015 https://doi.org/10.1109/JSSC.2014.2362854
  16. J.O. Lacruz, F.G. Herrero, J. Valls and D. Declercq, "One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes", IEEE Trans. Circuits Systems I: Regular Papers, vol. 62, no. 1, pp. 177-184, Jan. 2015. https://doi.org/10.1109/TCSI.2014.2354753