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Implementation of High Throughput LDPC Code Decoder for DVB-S2  

Kim, Seong-Woon (서강대학교 전자공학과 대학원 CAD & ES 연구실)
Park, Chang-Soo (서강대학교 전자공학과 대학원 CAD & ES 연구실)
Hwang, Sun-Young (서강대학교 전자공학과 대학원 CAD & ES 연구실)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.33, no.9A, 2008 , pp. 924-933 More about this Journal
Abstract
This paper proposes a novel LDPC code decoder architecture to improve throughput for DVB-S2, a second generation standard of ETSI for satellite broad-band applications. The proposed architecture clusters 360 bitnodes and checknodes into groups utilizing the property of IRA-LDPC code. Functional modules which perform calculations for bitnode groups and checknode groups have local memories and store the messages from the other type of functional modules connected by edges at their local memories. The proposed architecture can avoid memory conflicts by accessing stored messages sequentially, hence, increases throughput in the proposed DVB-S2 LDPC code decoder architecture. The proposed architecture was synthesized using the TSMC 90nm technology. Synthesis results show that throughput of the proposed architecture is improved by 104% and 478%, respectively, when compared with those of the architectures proposed by F. Kienle and J. Dielissen.
Keywords
LDPC; DVB-S2; Decoder; Local memory; High throughput;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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1 ETSI, Digital video broadcasting (DVB); Se cond generation framing structure, channel c oding and modulation systems for broadcasti ng, interactive services, news gathering and other broad-band satellite applications: EN 302 307 V1. 1.1, 2005
2 A. Morello and V. Mignone, "DVB-S2: The Second generation standard for satellite broa d-band services," Proceedings of the IEEE, Vol.94, No.1, pp.210-227, Jan. 2006   DOI   ScienceOn
3 T. Richardson and R. Urbanke, "Efficient encoding of low-density parity-check codes," IEEE Transactions on Information Theory, Vol.47, No.2, pp.638-656, Feb. 2001   DOI   ScienceOn
4 A. Blanksby and C. Howland, "A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder," IEEE Journal of Solid-State Circuits, Vol.37, No.3, pp.404-412, Mar. 2002   DOI   ScienceOn
5 R. Tanner, "A recursive approach to low complexity codes," IEEE Transactions on Information Theory, Vol.27, No.5, pp.533-547, Sep. 1981   DOI
6 배슬기, 김준성, 송홍엽, "순환 행렬과 eIRA부호를 이용한 효율적인 LDPC 부호화기 설계", 한국통신학회 논문지, 제 31권, 2C호, pp.123-129, 2006년 2월   과학기술학회마을
7 H. Jin, A. Khandekar, and R. McEliece, "Irregular Repeat-Accumulate Codes," in Proc. 2nd Int. Symp. on Turbo Codes & Related Topics, Brest, France, pp.1-8, sep. 2000
8 M. Gomes, G. Falcao, V. Silva, V. Ferreira, A. Sengo, and M. Falcao, "Flexible parallel architecture for DVB-S2 LDPC decoders," in Proc. GLOBECOM. IEEE, Washington DC, pp.3265-3269, Nov. 2007
9 F. Kienle, T. Brack, and N. Wehn, "A synthesizable IP core for DVB-S2 LDPC code decoding," in Proc. DATE, Munich, Germany, Vol.3, pp.100-105, Mar. 2005
10 J. Dielissen, A. Hekstra and V. Berg, "Lowcost LDPC decoder for DVB-S2," In Proc. DATE, Munich, Germany, Vol.2, pp.1-6, Mar. 2006
11 F. Kschischang and B. Frey, "Iterative decoding of compound codes by probability propagation in graphical models," IEEE Journal on Selected Areas in Communications, Vol.16, No.2, pp.219-230, Feb. 1998   DOI   ScienceOn
12 E. Yeo and V. Anantharam, "Iterative decoder architectures," IEEE Communications Magazine, Vol.41, No.8, pp.132-140, Aug. 2003
13 R. Gallager, "Low-density parity-check codes," IEEE Transactions on Information Theory, Vol.8, No.1, pp.21-28, Jan. 1962   DOI   ScienceOn
14 E. Yeo, P. Pakzad, B. Nikolic, and V. Anantharam, "High throughput low-density parity-check decoder architectures," in Proc. GLOBECOM. IEEE, San Antonio, TX, pp.3019-3 024, Nov. 2001
15 D. MacKay, "Good error-correcting codes based on very sparse matrices," IEEE Transactions on Information Theory, Vol.45, No.2, p p.399-431, Mar. 1999   DOI   ScienceOn