Implementation of High Throughput LDPC Code Decoder for DVB-S2

높은 throughput 성능을 갖는 DVB-S2 LDPC 부호의 복호기 구현

  • 김성운 (서강대학교 전자공학과 대학원 CAD & ES 연구실) ;
  • 박창수 (서강대학교 전자공학과 대학원 CAD & ES 연구실) ;
  • 황선영 (서강대학교 전자공학과 대학원 CAD & ES 연구실)
  • Published : 2008.09.30

Abstract

This paper proposes a novel LDPC code decoder architecture to improve throughput for DVB-S2, a second generation standard of ETSI for satellite broad-band applications. The proposed architecture clusters 360 bitnodes and checknodes into groups utilizing the property of IRA-LDPC code. Functional modules which perform calculations for bitnode groups and checknode groups have local memories and store the messages from the other type of functional modules connected by edges at their local memories. The proposed architecture can avoid memory conflicts by accessing stored messages sequentially, hence, increases throughput in the proposed DVB-S2 LDPC code decoder architecture. The proposed architecture was synthesized using the TSMC 90nm technology. Synthesis results show that throughput of the proposed architecture is improved by 104% and 478%, respectively, when compared with those of the architectures proposed by F. Kienle and J. Dielissen.

본 논문은 광대역 위성 서비스를 위한 유럽 전기통신 표준화기구의 2세대 표준인 DVB-S2에서 사용하는 LDPC 부호의 throughput을 증가시키기 위한 새로운 복호기 구조를 제안한다. 제안한 구조는 IRA 구조의 LDPC 부호가 가지는 특징을 이용해 360개의 비트노드와 체크노드를 각각 그룹핑한다. 노드 그룹을 구현한 연산모듈은 각각 로컬 메모리를 가지고 있고, 전달받은 메시지는 자신의 로컬 메모리에서만 읽는다. 제안한 구조는 메시지 라우팅 로직을 이용해 에지로 연결된 노드 그룹의 로컬 메모리에 메시지를 저장함으로써 메모리 충돌이 없고 순차적인 메모리 접근을 가능하게 하여 복호기의 throughput을 증가시킨다. 제안한 DVB-S2 LDPC 복호기 구조는 TSMC 90nm 공정으로 합성하였고 F Kienle과 J. Dielissen이 각각 제안한 기존의 구조보다 throughput이 각각 104%, 478%가 증가함을 확인하였다.

Keywords

References

  1. ETSI, Digital video broadcasting (DVB); Se cond generation framing structure, channel c oding and modulation systems for broadcasti ng, interactive services, news gathering and other broad-band satellite applications: EN 302 307 V1. 1.1, 2005
  2. A. Morello and V. Mignone, "DVB-S2: The Second generation standard for satellite broa d-band services," Proceedings of the IEEE, Vol.94, No.1, pp.210-227, Jan. 2006 https://doi.org/10.1109/JPROC.2005.861013
  3. R. Gallager, "Low-density parity-check codes," IEEE Transactions on Information Theory, Vol.8, No.1, pp.21-28, Jan. 1962 https://doi.org/10.1109/TIT.1962.1057683
  4. R. Tanner, "A recursive approach to low complexity codes," IEEE Transactions on Information Theory, Vol.27, No.5, pp.533-547, Sep. 1981 https://doi.org/10.1109/TIT.1981.1056404
  5. D. MacKay, "Good error-correcting codes based on very sparse matrices," IEEE Transactions on Information Theory, Vol.45, No.2, p p.399-431, Mar. 1999 https://doi.org/10.1109/18.748992
  6. F. Kschischang and B. Frey, "Iterative decoding of compound codes by probability propagation in graphical models," IEEE Journal on Selected Areas in Communications, Vol.16, No.2, pp.219-230, Feb. 1998 https://doi.org/10.1109/49.661110
  7. T. Richardson and R. Urbanke, "Efficient encoding of low-density parity-check codes," IEEE Transactions on Information Theory, Vol.47, No.2, pp.638-656, Feb. 2001 https://doi.org/10.1109/18.910579
  8. 배슬기, 김준성, 송홍엽, "순환 행렬과 eIRA부호를 이용한 효율적인 LDPC 부호화기 설계", 한국통신학회 논문지, 제 31권, 2C호, pp.123-129, 2006년 2월
  9. M. Gomes, G. Falcao, V. Silva, V. Ferreira, A. Sengo, and M. Falcao, "Flexible parallel architecture for DVB-S2 LDPC decoders," in Proc. GLOBECOM. IEEE, Washington DC, pp.3265-3269, Nov. 2007
  10. H. Jin, A. Khandekar, and R. McEliece, "Irregular Repeat-Accumulate Codes," in Proc. 2nd Int. Symp. on Turbo Codes & Related Topics, Brest, France, pp.1-8, sep. 2000
  11. F. Kienle, T. Brack, and N. Wehn, "A synthesizable IP core for DVB-S2 LDPC code decoding," in Proc. DATE, Munich, Germany, Vol.3, pp.100-105, Mar. 2005
  12. J. Dielissen, A. Hekstra and V. Berg, "Lowcost LDPC decoder for DVB-S2," In Proc. DATE, Munich, Germany, Vol.2, pp.1-6, Mar. 2006
  13. E. Yeo and V. Anantharam, "Iterative decoder architectures," IEEE Communications Magazine, Vol.41, No.8, pp.132-140, Aug. 2003
  14. E. Yeo, P. Pakzad, B. Nikolic, and V. Anantharam, "High throughput low-density parity-check decoder architectures," in Proc. GLOBECOM. IEEE, San Antonio, TX, pp.3019-3 024, Nov. 2001
  15. A. Blanksby and C. Howland, "A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder," IEEE Journal of Solid-State Circuits, Vol.37, No.3, pp.404-412, Mar. 2002 https://doi.org/10.1109/4.987093