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LDPC Decoder Architecture for High-speed UWB System  

Choi, Sung-Woo (한국전자통신연구원 인터넷연구부문 무선통신연구부)
Lee, Woo-Yong (한국전자통신연구원 인터넷연구부문 무선통신연구부)
Chung, Hyun-Kyu (한국전자통신연구원 인터넷연구부문 무선통신연구부)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.35, no.3C, 2010 , pp. 287-294 More about this Journal
Abstract
MB-OFDM UWB system will adopt LDPC codes to enhance the decoding performance with higher data rates. In this paper, we will consider algorithm and architecture of the LDPC codes in MB-OFDM UWB system. To suggest the hardware efficient LDPC decoder architecture, LLR(log-likelihood-ration) calculation algorithms and check node update algorithms are analyzed. And we proposed the architecture of LDPC decoder for the high throughput application of Wimedia UWB. We estimated the feasibility of the proposed architecture by implementation in a FPGA. The implementation results show our architecture attains higher throughput than other result of QC-LDPC case. Using this architecture, we can implement LDPC decoder for high throughput transmission, but it is 0.2dB inferior to the BP algorithm.
Keywords
UWB; LDPC; Min-sum; Layered;
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