References
- "Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for High Rate Wireless Personal Area Networks (WPANs): Amendment 2: Millimeter-wave based Alternative Physical Layer Extension," 2008. IEEE P802.15.3c/D04
- L. Liu and C.-J. R. Shi, "Sliced message passing: High throughput over- lapped decoding of high-rate low-density parity-check codes," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 11, pp. 3697-3710, Nov. 2008. https://doi.org/10.1109/TCSI.2008.926995
- 나영헌, 신경욱, "IEEE 802.11n용 다중모드 Layered LDPC 복호기," 대한전자공학회 논문지, 제48권 SD편, 제 11호, 18-26쪽, 2011년 11월.
- M. Mansour and N. Shanbhag, "High-throughput LDPC decoders," IEEE Trans. VLSI Syst., vol. 11, no. 6, pp. 976-996, Dec. 2003. https://doi.org/10.1109/TVLSI.2003.817545
- D. E. Hocevar, "A reduced complexity decoder architecture via layered decoding of LDPC codes," IEEE Workshop on Signal Processing Systems (SiPS), pp. 107-112, Oct. 2004.
- S. Kim, G. E. Sobelman, and H. Lee, "Flexible LDPC decoder architecture for high-throughput applications," in Proc. IEEE Asia Pacific Conf. Circuits Syst. (APCCAS), Macao, China, pp. 45-48, Nov. 2008.
- Z. Cui, Z. Wang, and Y. Liu, "High-throughput layered LDPC decoding architecture," IEEE Trans. VLSI Syst., vol. 17, no. 4, pp. 582-587, April 2009. https://doi.org/10.1109/TVLSI.2008.2005308
- S. Kim, G. E. Sobelman, and H. Lee, "A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes," IEEE Trans. VLSI Syst., vol. 19, no. 6, pp. 1099-1103, June 2011. https://doi.org/10.1109/TVLSI.2010.2043965
- S. Zhao, Z. Farhad, "On implementation of Min-Sum algorithm and its modifications for decoding Low-Density Parity-Check (LDPC) codes," IEEE Trans. Commun., vol. 53, no. 4, pp. 549-554, Aug. 2005. https://doi.org/10.1109/TCOMM.2004.836563
-
X.-Y. Shih, C.-Z. Zhan, C.-H. Lin, and A.-Y. Wu, "An 8.29 mm2 52mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in
$0.13{\mu}m$ CMOS Process," IEEE J. Solid-State Circuits, vol. 43, no. 3, pp. 672-683, March 2008. https://doi.org/10.1109/JSSC.2008.916606 - S. H. Kang and I. C. Park, "Loosely coupled memory-based decoding architecture for low density parity check codes," IEEE Trans. Circuits Syst. I, vol. 53, no. 5, pp. 1045-1056, May 2006. https://doi.org/10.1109/TCSI.2005.862181
- S. Hung, S. Yen, C. Chen, H. Chnag, S. Jou, C. Lee, "A 5.7Gbps row-based layered scheduling LDPC decoder for IEEE 802.15.3c applications", 2010 IEEE Asian Solid State Circuits Conference (A-SSCC), Nov. 2010.
- J. Sha, J. Lin, Z. Wang, L. Li, M. Gao, "LDPC decoder design for high rate wireless personal area networks", IEEE Trans. Consumer Electronics. vol. 55, no. 2, pp. 455-460, May 2009. https://doi.org/10.1109/TCE.2009.5174407
- Z. Cui, Z. Wang, and X. Wang, "Reducedcomplexity column-layered decoding and implementation for LDPC codes," IET Commun., vol. 5, no.15, pp. 2177-2186, Oct. 2011. https://doi.org/10.1049/iet-com.2010.1002
Cited by
- Pipeline-Aware QC-IRA-LDPC Code and Efficient Decoder Architecture vol.51, pp.10, 2014, https://doi.org/10.5573/ieie.2014.51.10.072