• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1205-1208
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• 2003

본 논문에서는 분할된 스캔을 이용한 저전력 BIST 구조를 제안한다. 제안하는 BIST는 내부 스캔 패스를 회로의 구조적인 정보와 테스트 패턴 집합의 특성에 따라 4개의 스캔 패스로 분할하고 일부 스캔 패스에만 입력패턴이 인가되도록 설계하였다. 따라서 테스트 패턴 입력 시에 스캔 패스로의 쉬프트 동작 수를 줄임으로써 회로 내부의 전체 상태천이 수를 줄일 수 있다. 또한 4개로 분할되는 스캔패스의 길이를 고려하여 각 스캔 패스에 대해 1/4의 속도로 낮춰진 테스트 클럭을 인가함으로써 전체 회로의 전력 소모를 줄일 수 있도록 하였다. ISCAS89 벤치마크 회로에 대한 실험을 통하여 제안하는 BIST 구조가 기존 BIST 구조에 비해 최대 21%까지 전력소모를 줄일 수 있음을 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.63-71
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• 2003

IDDQ testing is indispensable in improving Duality and reliability of CMOS VLSI circuits. But the major problem of IDDQ testing is slow testing speed due to time-consuming IDDQ current measurement. So one requirement is to reduce the number of target faults or to make the test sets compact in fault model. In this paper, we consider equivalent fault collapsing for transistor short faults, a fault model often used in IDDQ testing and propose an efficient algorithm for reducing the number of faults that need to be considered by equivalent fault collapsing. Experimental results for ISCAS benchmark circuits show the effectiveness of the proposed method.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2008.04a
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• pp.288-291
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• 2008

본 논문은 실수 진화 알고리즘에 대해서 가상의 클러스터를 이용한 재조합 연산자 및 새로운 세대차 모델을 소개한다. 가상 클러스터의 자가 적응적인 크기 변화를 통해 자손의 생성범위를 적절히 조절하고, 선택과 대치를 포함한 진화방식을 개선하여 효율적인 세대차 크기를 구함으로서, 개체의 다양성 유지 및 탐색성능의 향상을 꾀하였다. 제안된 방법을 벤치마크 테스트 문제에 적용하여 G3 알고리즘과 CMA-ES 등과 성능을 비교하였다.

• 전자공학회논문지 IE
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• v.45 no.3
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• pp.5-12
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• 2008

We propose efficient scan testing method capable of reducing the test data and power dissipation for digital logic circuits. The proposed testing method is based on a hybrid run-length encoding which reduces test data storage on the tester. We also introduce modified Bus-invert coding method and scan cell design in scan cell reordering, thus providing increased power saving in scan in operation. Experimental results for ISCAS'89 benchmark circuits show that average power of 96.7% and peak power of 84% are reduced on the average without fault coverage degrading. We have obtained a high reduction of 78.2% on the test data compared the existing compression methods.

• Journal of the Korea Computer Industry Society
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• v.6 no.3
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• pp.559-566
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• 2005

ALTIBASE is the relational main memory DBMS that enables us to develop the high performance and fault tolerant applications. It guarantees the short and predictable execution time as well as the basic functionality of conventional disk-based DBMS. We present the overview of system architecture and the performance analysis with respect to the various design choices. The assorted experiments are performed under the various environments. The results of TPC-H and Wisconsin benchmark tests are described. We illustrate the various performance comparisons under the various index mechanisms, the replication models, the transaction durabilities, and the application structures. A performance study shows the ALTIBASE system can be applied to the wide area of industrial DBMS fields.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.1
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• pp.235-244
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• 1999

This Paper proposes a new compaction algorithm for IDDQ testing in CMOS Circuits. A primary test pattern is generated by the primitive fault pattern which is able to detect GOS(gate-oxide short) and the bridging faults in an internal primitive gate. The new algorithm can reduce the number of the test vectors by decreasing the don't care(X) in the primary test pattern. The controllability of random number is used on processing of the backtrace together four ones of heuristics. The simulation results for the ISCAS-85 benchmark circuits show that the test vector reduction is more than 45% for the large circuits on the average compared to static compaction algorithms.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.6
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• pp.361-368
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• 2002

This paper presents a new data path synthesis algorithm which takes into account simultaneously three important design criteria: testability, design area, and total execution time. We define a goodness measure on the testability of a circuit based on three rules of thumb introduced in prior work on synthesis for testability. We then develop a stepwise refinement synthesis algorithm which carries out the scheduling and allocation tacks in an integrated fashion. Experimental results for benchmark and other circuit examples show that we are able to enhance the testability of circuits with very little overheads on design area and execution time.

• Journal of Internet Computing and Services
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• v.4 no.3
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• pp.31-37
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• 2003

In this paper, an efficient non-scan design-for-testability (DFT) method for finite state machine(FSM) is proposed. The proposed method always guarantees short test pattern generation time and complete fault efficiency. It has a lower area overhead than full-scan and other non-scan DFT methods and enables to apply test patterns at-speed. The efficiency of the proposed method is demonstrated using well-known MCNC'91 FSM benchmark circuits.

• The Journal of the Korea institute of electronic communication sciences
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• v.5 no.4
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• pp.443-449
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• 2010

Current testing is an effective method which offers higher fault detection and diagnosis capabilities than voltage testing. Since current testing requires much longer testing time than voltage testing, it is important to note that a fault is untestable if the two nodes have same values at all times. In this paper, we present an object oriented fault detection scheme for various fault models using current testing. Experimental results for ISCAS benchmark circuits show the effectiveness of the proposed method in reducing the number of faults and its usefulness in various fault models.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.65-70
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• 2004

The SOC(System on Chip) testing has required the core re-use methodology and the efficiency of test method because of increase of its cost. The goal of SOC testing is to minimize the testing time, area overhead, and power consumption during testing. Prior research has concentrated on only one aspect of the test core wrapper design problem at a test time. Our research is concentrated on optimization of test time and area overhead for the core test wrapper, which is one of the important elements for SOC test architecture. In this paper, we propose an efficient wrapper design algorithm that improves on earlier approaches by also reducing the TAM(Test Access Mechanism) width required to achieve these lower testing times.