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Stepwise Refinement Data Path Synthesis Algorithm for Improved Testability  

Kim, Tae-Hwan (Dept. of Electronic Computer Science, Korea Advanced Institute of Science and Technology)
Chung, Ki-Seok (Dept. of Computer Engineering, Hongik University)
Publication Information
Journal of KIISE:Computer Systems and Theory / v.29, no.6, 2002 , pp. 361-368 More about this Journal
Abstract
This paper presents a new data path synthesis algorithm which takes into account simultaneously three important design criteria: testability, design area, and total execution time. We define a goodness measure on the testability of a circuit based on three rules of thumb introduced in prior work on synthesis for testability. We then develop a stepwise refinement synthesis algorithm which carries out the scheduling and allocation tacks in an integrated fashion. Experimental results for benchmark and other circuit examples show that we are able to enhance the testability of circuits with very little overheads on design area and execution time.
Keywords
Architecture design; testing; design automation;
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1 C. A. Papachristou, S. Chju, and H. Harmanani, 'Data Path Synthesis Method for Self-Testable Designs,' Proc. Design Automation Conference, pp.378-384, 1991   DOI
2 C. A. Papachristou, 'Rescheduling Transformation for High Level Synthesis,' Proc. International Symposium on Circuits and Systems, pp.766-769, 1989   DOI
3 A. Ghosh, S. Devadas, A. R. Newton, 'Test Generation for Highly Sequential Circuits,' Proc. International Conference on Computer-Aided Design, pp.362-365, 1989   DOI
4 A. Mujumdar, K. Saluja, and R. Jain, 'Incorporating Performance and Testability Constraints during Binding in High-level Synthesis,' IEEE Trans. on CAD, Vol.15, No.10, October 1996   DOI   ScienceOn
5 I. Parulkar, S. Gupta, and M. A. Breuer, 'Data path allocation for synthesizing RTL designs with Low BlST area overhead,' Proc. Design Automation Conference, pp.395-401, 1995   DOI
6 I. Parulkar, S. Gupta, and M. A. Breuer, 'Introducing Redundant Computations in a Behavior for Reducing BIST Resources,' Proc. Design Automation Conference, pp.548-553, 1998   DOI
7 I. Parulkar, S. Gupta, and M. A. Breuer, 'Scheduling and Module Assignment for Reducing BIST Resources,' Proc. Design, Automation and Test in Europe, pp. 66-73 1998   DOI
8 L. Avra, 'Allocation and Assignment in High-Level Synthesis for Self-testable Data Paths,' Proc. International Test Conference, pp.463-472, 1991
9 L. Stok, 'An Exact Polynomial Time Algorithm for Module Allocation,' Proc. The fifth Int. Workshop on High-Level Synthesis, pp.69-76, 1991
10 F. J. Kurdahi and A. C. Parker, 'REAL: A Program for Register Allocation,' Proc. 24th Design Automation Conference, pp.210-215, 1987   DOI
11 E. M. Sentovich, et al., 'Sequential Circuit Design using Synthesis and Optimization,' Proc. International Conference on Computer Design, pp.328-333, 1992   DOI
12 T-C. Lee, W. H. Wolf, and N. K. Jha, 'Behavioral Synthesis for Easy Testability in Data Path Scheduling,' Proc. International Conference on Computer-Aided Design, pp.616-619, 1992   DOI
13 T-C. Lee et al., 'Behavioral Synthesis for Easy Testability in Data Path Allocation,' Proc. International Conference on Computer Design, pp.29-32, 1992