1 |
J. M. Soden, C. F. Hawkins, R K. Gulati, W. Mao, "IDDQ Testing : A Review," Journal of Electronic Testing, vol 3, no 4, pp. 291-303, 2004.
|
2 |
홍성제 외, 테스팅 및 테스팅을 고려한 설계, 홍릉과학출판사, 2001.
|
3 |
R. Rajsuman, IDDQ Testing for CMOS VLSI, Artech House, 1994.
|
4 |
W. Mao and R. K. Gulati, "QUIETEST: A Quiescent Current Testing Methodology for Detecting Leakage Faults," Proc. ICCAD'90, pp. 280-283, 1990.
|
5 |
S. Chakravarty and S. T. Zachariah, "STBM: A Fast Algorithm to Simulate IDDQ Tests for Leakage Faults," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 5, pp. 568-576, May 2000.
DOI
ScienceOn
|
6 |
L. T. Wang, C. W. Wu, X. Wen, VLSI Test Principles and Architectures: Design for Testability, Elsevier, 2006.
|
7 |
P. J. Thadikaran, "Evaluation, selection and generation of IDDQ tests," PHD. Thesis, Department of Computer Science, State University of New York, 1996.
|
8 |
T. Shinogi and T. Hayashi, "An iterative improvement method for generating compact tests for IDDQ testing of bridging faults," IEICE Trans. INF & SYST., Vol. E81-D. No. 7, July 1998.
|
9 |
T. Lee, I. N. Hajj, E. M. Rudnick, J. H. Patel, "Genetic-algorithm based test generation for current testing of bridging faults in CMOS VLSI circuits," IEEE VLSI Test Symposium, pp. 456-462, 1996.
|
10 |
X. Wen, H. Tamamoto and K. Kinoshita, "IDDQ Test Vector Selection for Transistor Short Fault Testing," System and Computers in Japan, vol. 28, no. 5, 1997.
|