Stepwise Refinement Data Path Synthesis Algorithm for Improved Testability

개선된 테스트 용이화를 위한 점진적 개선 방식의 데이타 경로 합성 알고리즘

  • Kim, Tae-Hwan (Dept. of Electronic Computer Science, Korea Advanced Institute of Science and Technology) ;
  • Chung, Ki-Seok (Dept. of Computer Engineering, Hongik University)
  • 김태환 (한국과학기술원 전자전산학과) ;
  • 정기석 (홍익대학교 컴퓨터공학과)
  • Published : 2002.06.01

Abstract

This paper presents a new data path synthesis algorithm which takes into account simultaneously three important design criteria: testability, design area, and total execution time. We define a goodness measure on the testability of a circuit based on three rules of thumb introduced in prior work on synthesis for testability. We then develop a stepwise refinement synthesis algorithm which carries out the scheduling and allocation tacks in an integrated fashion. Experimental results for benchmark and other circuit examples show that we are able to enhance the testability of circuits with very little overheads on design area and execution time.

본 논문은 세 가지 중요한 설계 기준인 테스트 용이화, 설계 면적, 및 전체 수행 시간을 동시에 고려한 새로운 데이터 경로 합성 알고리즘을 제시한다. 우리는 테스트 용이화를 위한 선행 연구들에서 제시한 세 가지 기초적 척도들에 근거하여 새로운 테스트 용이화의 우수성에 대한 척도를 정의한다. 이 척도를 이용하여, 스케쥴링과 할당의 통합된 형태의, 단계식이며 점진적 개선을 통한, 합성 알고리즘을 제시한다. 벤치마크 설계와 다른 회로의 예를 통한 실험에서, 우리는 설계 면적과 수행 시간에 대해 매우 적은 추가 부담으로, 회로의 테스트 용이화가 향상됨을 보인다.

Keywords

References

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