• Proceedings of the KAIS Fall Conference
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• 2009.05a
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• pp.255-258
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• 2009

최근 EDA 툴의 기술적인 향상과 반도체 공정의 발달로 IC 설계자들은 RISC 프로세서, DSP 프로세서, 메모리 등 많은 IP가 하나로 집적되는 SoC구조가 가능해졌다. 하지만 기존에 사용되는 대부분의 SoC는 공유버스 구조를 가지고 있어, 병목현상이 발생하는 문제점을 가진다. 이러한 문제점은 SoC 내부의 IP들이 많을수록 SoC 플랫폼의 전체 성능이 저하되어, CPU 자체의 속도보다는 효율적인 통신에 의해 성능이 좌우된다. 본 논문에서는 공유버스의 단점인 병목현상을 줄이고 성능을 향상시키기 위하여 크로스바 스위치버스 구조를 제안한다. OpenRISC 프로세서, VGA/LCD 제어기, AC97 제어기, 디버그 인터페이스, 메모리 인터페이스로 구성되는 SoC 플랫폼의 WISHBONE 온칩 공유버스 구조와 크로스바 스위치 버스 구조의 성능을 비교한 결과, 기존의 공유버스보다 26.58%의 성능이 향상됨을 확인하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2006.05a
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• pp.1175-1178
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• 2006

반도체 공정 자동화를 위해 SEMI에서 제창한 표준 규약인 SECS Protocol은 메시지 전송을 위한 규약인 SECS-I과 HSMS, 실제 통신되는 메시지에 대한 규약인 SECS-II로 구성된다. 하지만 SECS-I에서는 통신속도가 느리고, 근거리 통신만 가능하고, 호스트 컴퓨터와 설비간의 연결이 1:1로 이루어져야 하는 등 여러 가지 문제점도 있고 요즘에는 TCP/IP 기반의 HSMS Protocol 장비가 나오기 때문에 SECS-I을 HSMS로 변환시켜 주는 장치가 필요하다. 본 논문에서는 SECS-I 지원용으로 제작된 설비라도 HSMS를 지원할 수 있도록 하여 HSMS가 갖는 여러 가지 장점을 갖도록 하는 SECS-I/HSMS 변환방법에 관해 살펴본다.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.29 no.1 s.232
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• pp.96-106
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• 2005

An integrated single-wafer processing tool, composed of multiple single wafer processing modules, transfer robots, and load locks, has complex routing sequences, and often has critical post-processing residency constraints. Scheduling of these tools is an intricate problem, and testing schedulers with actual tools requires too much time and cost. The Single Wafer Processor (SWP) simulator presented in this paper is to validate an on-line scheduler, and evaluate performance of integrated single-wafer processing tools before the scheduler is actually deployed into real systems. The data transfer between the scheduler and the simulator is carried out with TCP/IP communication using messages and files. The developed simulator consists of six modules, i.e., GUI (Graphic User Interface), emulators, execution system, module managers, analyzer, and 3D animator. The overall framework is built using Microsoft Visual C++, and the animator is embodied using OpenGL API (Application Programming Interface).

• Proceeding of EDISON Challenge
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• 2014.03a
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• pp.467-471
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• 2014

유기 반도체 물질로서 활발히 연구되고 있는 CuPC의 기체 및 고체상에 대한 전자구조 분석을 진행하였다. CuPC는 기체상에서는 4 eV 이상의 큰 HOMO-LUMO gap을 가지고 있지만 고체가 되면 ~2 eV 정도의 gap을 나타내게 된다는 것을 밝혔다. 특히 GW 계산을 이용하여 고체에서 전자의 screening 효과는 IP와 EA를 기체에 비해 상당히 변화시킨다는 것을 알아냈고 이는 CuPC와 같은 유기 분자로 이루어진 고체의 전자구조 결정에 polarizable medium을 잘 기술하는 것이 중요한 역할을 한다는 것을 발견하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.712-720
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• 2001

Algorithms from the research of the layout migration were proposed in the paper. These are automatic recognition algorithm for the VLSI devices from it, graph based construction algorithm to maintain the constraints, dependencies, and design rule between the devices, and high speed compaction algorithm to reduce size of the VLSI area and reuse the design with compacted size for the new technology. Also, this paper describes that why proposed algorithms are essential for the era of the SoC (System on a Chip), design reuse, and IP DB, which are the big concerns in these days. In addition to introduce our algorithms, the benchmark showed that our performance is superior by 27 times faster than that of the commercial one, and has better efficiency by 3 times in disk usage.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.6
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• pp.742-750
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• 2018

In this paper, in order to enable zero-layer FTP cell using only 5V MOS devices on the basis of $0.13{\mu}m$ BCD process, the tunnel oxide thickness is used as the gate oxide thickness of $125{\AA}$ of the 5V MOS device at 82A. The HDNW layer, which is the default in the BCD process, is used. Thus, the proposed zero layer FTP cell does not require the addition of tunnel oxide and DNW mask. Also, from the viewpoint of memory IP design, a single memory structure which is used only for trimming analog circuit of PMIC chip is used instead of the dual memory structure dividing into designer memory area and user memory area. The start-up circuit of the BGR (Bandgap Reference Voltage) generator circuit is designed to operate in the voltage range of 1.8V to 5.5V. On the other hand, when the 64-bit FTP memory IP is powered on, the internal read signal is designed to maintain the initial read data at 00H. The layout size of the 64-bit FTP IP designed using the $0.13-{\mu}m$ Magnachip process .is $485.21{\mu}m{\times}440.665{\mu}m$($=0.214mm^2$).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.3
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• pp.567-574
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• 2015

In this paper, a 50ns 256-kb EEPROM IP for MCU (micro controller unit) ICs is designed. The speed of data sensing is increased in the read mode by using a proposed DB sensing circuit of differential amplifier type which uses the reference voltage, and the switching speed is also increased by reducing the total DB parasitic capacitance as a distributed DB structure is separated into eight. Also, the access time is reduced reducing a precharging time of BL in the read mode removing a 5V NMOS transistor in the conventional RD switch, and the reliability of output data can be secured by obtaining the differential voltage (${\Delta}V$) between the DB and the reference voltages as 0.2*VDD. The access time of the designed 256-kb EEPROM IP is 45.8ns and the layout size is $1571.625{\mu}m{\times}798.540{\mu}m$ based on MagnaChip's $0.18{\mu}m$ EEPROM process.

• Journal of IKEEE
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• v.13 no.2
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• pp.101-107
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• 2009

Growth in the VLSI process and design technology is resulting into a continuous increase in the number of IPs on a chip to form a system. Because of many IPs on a single chip, efficient communication between IPs is essential. We propose a dynamically reconfigurable 3-layer bus structure which can adapt to the pattern of data transmission to achieve an efficient data communication between various IPs. The proposed 3-layer bus can be reconfigured to multi-single bus mode, and single-multi bus mode, thus providing the benefits of both single-bus and multi-bus modes. Experimental results show that the flexibility of the proposed bus structure can reduce data transmission time compared to the conventional fixed bus structure. We incorporated the proposed bus structure in a JPEG system and verified that the proposed structure achieved an average of 22% improvement in time over the conventional fixed bus structure.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.439-442
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• 2003

In this paper, a system that implementation of Access Control System Using Biometric System. Biometrics is science which deals with verifying or recognizing using physiological or behavioral characteristic Access Control System uses Biometric system to make an access control system. Biometrics goes under the study of bio-recognition or bio-measurement. It is a technology or study that identifies individuals using one's Biometric character. Access control system is a system used to identify one's entrance and exit, personal management, and security. Access control system can be joined with Biometric system to produce easier use and more sufficient effects. Access control system using Wiegand (Data Format) signal output, can replace earlier RF Card systems and make an access control (security) system. It uses RS-232, Rs-422 or TCP/IP type communication with the computer so an embedded system can be controlled using the software.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.494-498
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• 2004

In this paper, a system that implementation of Access Control System Using Biometric System. Biometries is science which deals with verifying or recognizing using physiological or behavioral characteristic Access Control System uses Bionietric system to make an access control system. Biometrics goes under the study of bio-recognition or bio-measurement. It is a technology or study that identifies individuals using one's Biometric character. Access control system is a system used to identify one's entrance and exit, personal management, and security. Access control system can be joined with Biometric system to produce easier use and more sufficient effects. Access control system using Weigand (Data format) signal output, can replace earlier RF Card systems and make an access control (security) system. It uses RS-232, Rs-422 or TCP/IP type communication with the computer so an embedded system can be controlled using the software.