• 마이크로전자및패키징학회지
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• 제25권1호
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• pp.41-45
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• 2018

기술의 발전과 전자기기의 소형화와 함께 반도체의 크기는 점점 작아지고 있다. 이와 동시에 반도체 성능의 고도화가 진행되면서 입출력 단자의 밀도는 높아져 패키징의 어려움이 발생하였다. 이러한 문제를 해결하기 위한 방법으로 산업계에서는 팬아웃 웨이퍼 레벨 패키지(FO-WLP)에 주목하고 있다. 또한 FO-WLP는 다른 패키지 방식과 비교해 얇은 두께, 강한 열 저항 등의 장점을 가지고 있다. 하지만 현재 FO-WLP는 생산하는데 몇 가지 어려움이 있는데, 그 중 한가지가 웨이퍼의 휨(Warpage) 현상의 제어이다. 이러한 휨 변형은 서로 다른 재료의 열팽창계수, 탄성계수 등에 의해 발생하고, 이는 칩과 인터커넥트 간의 정렬 불량 등을 야기해 대량생산에 있어 제품의 신뢰성 문제를 발생시킨다. 이러한 휨 현상을 방지하기 위해서는 패키지 재료의 물성과 칩 사이즈 등의 설계 변수의 영향에 대해 이해하는 것이 매우 중요하다. 이번 논문에서는 패키지의 PMC 과정에서 칩의 두께와 EMC의 두께가 휨 현상에 미치는 영향을 유한요소해석을 통해 알아보았다. 그 결과 특정 칩과 EMC가 특정 비율로 구성되어 있을 때 가장 큰 휨 현상이 발생하는 것을 확인하였다.

• 대한기계학회논문집A
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• 제39권10호
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• pp.1011-1019
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• 2015

Insulated gate bipolar transistor (IGBT) 소자는 전동차, 항공기 및 전기 자동차에 가장 많이 사용되는 고전압, 고전력용 전력 반도체이다. 그러나 IGBT 전력소자는 동작 시 발열 온도가 매우 높고, 이로 인해, IGBT 소자의 신뢰성 및 성능에 큰 영향을 미치고 있다. 따라서 발열 문제를 해결하기 위한 IGBT 모듈 패키지의 방열 설계는 매우 핵심적인 기술이며, 특히, 소자가 동작 한계 온도에 올라가지 않도록 방열 설계를 적절히 수행하여야 한다. 본 논문에서는 전동차에 사용되는 1200 A, 3.3 kV 급 IGBT 모듈 패키지의 열 특성에 대해 수치해석을 이용하여 분석하였다. IGBT 모듈 패키지에 사용되는 다양한 재료 및 소재의 두께에 대한 영향을 분석하였으며, 실험계획법을 이용한 최적화 설계를 수행하였다. 이를 통하여 열 저항을 최소화하기 위한 최적의 방열 설계 가이드 라인을 제시하고자 하였다.

• 반도체디스플레이기술학회지
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• 제21권4호
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• pp.45-49
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• 2022

Through Silicon Via (TSV) is a technology that interconnects chips through silicon vias. TSV technology can achieve shorter distance compared to wire bonding technology with excellent electrical characteristics. Due to this characteristic, it is currently being used in many fields that needs faster communication speed such as memory field. However, there is performance degradation issue on TSV technology due to the parasitic capacitance. To deal with this problem, in this study, the parasitic capacitance with TSV design factors is analyzed using commercial tool. TSV design factors were set in three categories: size, aspect ratio, pitch. Each factor was set by dividing the range with TSV used for memory and package. Ansys electronics desktop 2021 R2.2 Q3D was used for the simulation to acquire parasitic capacitance data. DOE analysis was performed based on the reaction surface method. As a result of the simulation, the most affected factors by the parasitic capacitance appeared in the order of size, pitch and aspect ratio. In the case of memory, each element interacted, and in the case of package, it was confirmed that size * pitch and size * aspect ratio interact, but pitch * aspect ratio does not interact.

• 한국공작기계학회논문집
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• 제12권2호
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• pp.65-70
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• 2003

In this study, researchers developed the estimative algorithm for artificial defect in semiconductor packages and performed it by pattern recognition technology. For this purpose, the estimative algorithm was included that researchers made software with MATLAB. The software consists of some procedures including ultrasonic image acquisition, equalization filtering, Self-Organizing Map and Backpropagation Neural Network. Self-organizing Map and Backpropagation Neural Network are belong to methods of Neural Networks. And the pattern recognition technology has applied to classify three kinds of detective patterns in semiconductor packages : Crack, Delamination and Normal. According to the results, we were confirmed that estimative algerian was provided the recognition rates of 75.7% (for Crack) and 83.4% (for Delamination) and 87.2 % (for Normal).

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2016년도 추계학술대회 논문집
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• pp.165.2-165.2
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• 2016

현재, 솔더범프용 주석계 도금액의 필수성분인 산화방지제의 경우, 국내외 경쟁사에서는 가격 및 성능이 우수한 벤젠/페놀 계열을 적용 중이다. 그러나, 최근 대형 고객사에서 페놀류 산화방지지제를 환경규제물질로 규정함에 따라, 자사에서는, 특허 이슈 해소 가능한 친환경 대체 산화방지제 개발을 해오고 있다. 본 연구에서는, 반도체 패키지용 주석계 도금액의 산화방지제 종류와 농도에 따른 주요 특성 (Particle, 전류 효율, 안정성 (변색, 침전 외), 범프 두께의 편차, 감광제의 침해, Reflow 후 빈공간 등)에 대하여 살펴보았다.

• 한국공작기계학회논문집
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• 제15권6호
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• pp.82-87
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• 2006

Availability of defect test algorithm that recognizes exact and standardized defect information in order to fundamentally resolve generated defects in industrial sites by giving artificial intelligence to SAT(Scanning Acoustic Tomograph), which previously depended on operator's decision, to find various defect information in a semiconductor package, to decide defect pattern, to reduce personal errors and then to standardize the test process was verified. In order to apply the algorithm to the lately emerging Neural Network theory, various weights were used to derive results for performance advancement plans of the defect test algorithm that promises excellent field applicability.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2003년도 추계학술대회
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• pp.1442-1447
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• 2003

Computer is a very powerful machine which is widely using for data processing, DB construction, peripheral device control, image processing etc. Consequently, many researches and developments have progressed for high performance processing unit, and other devices. Especially, the core units such as semiconductor parts are rapidly growing so that high-integration, high-performance, microminiat turization is possible. The packaging in the semiconductor industry is very important technique to de determine the performance of the system that the semiconductor is used. In this paper, the inspection of the inner defects such as delamination, void, crack, etc. in the semiconductor packages is studied. ESPI which is a non-contact, non-destructive, and full-field inspection method is used for the inner defect inspection and its results are compared with that of C-Scan method.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2002년도 추계학술대회 논문집
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• pp.345-350
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• 2002

In this study, researchers classifying the artificial flaws in semiconductor packages are performed by pattern recognition technology. For this purposes, image pattern recognition package including the user made software was developed and total procedure including ultrasonic image acquisition, equalization filtration, binary process, edge detection and classifier design is treated by Backpropagation Neural Network. Specially, it is compared with various weights of Backpropagation Neural Network and it is compared with threshold level of edge detection in preprocessing method fur entrance into Multi-Layer Perceptron(Backpropagation Neural network). Also, the pattern recognition techniques is applied to the classification problem of defects in semiconductor packages as normal, crack, delamination. According to this results, it is possible to acquire the recognition rate of 100% for Backpropagation Neural Network.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2005년도 추계학술대회 논문집
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• pp.721-726
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• 2005

In this study, researchers classifying the artificial flaws in semiconductor. packages are performed by pattern recognition technology. For this purposes, image pattern recognition package including the user made software was developed and total procedure including ultrasonic image acquisition, equalization filtration, binary process, edge detection and classifier design is treated by Backpropagation Neural Network. Specially, it is compared with various weights of Backpropagation Neural Network and it is compared with threshold level of edge detection in preprocessing method for entrance into Multi-Layer Perceptron(Backpropagation Neural network). Also, the pattern recognition techniques is applied to the classification problem of defects in semiconductor packages as normal, crack, delamination. According to this results, it is possible to acquire the recognition rate of 100% for Backpropagation Neural Network.

• 반도체디스플레이기술학회지
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• 제20권4호
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• pp.167-170
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• 2021

Integrated passive device (IPD) technology has emerged with the need for 5G. In order to integrate and miniaturize capacitors inside IPD, various studies are actively performed using high-k materials and trench structures. In this paper, an EM(Electromagnetic) simulation study was performed by applying an oxide dielectric to the capacitors having a various trench type structures. Commercially available materials HfO₂, Al₂O₃, and Ta₂O₅ are applied to non, circle, trefoil, and quatrefoil type trench structures to confirm changes in each material or structure. As a result, the bigger the capacitor area and the higher dielectric constant of the oxide dielectric, the insertion loss tended to decrease.