• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.841-843
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• 2005

최근 64비트 CPU의 시장 출시가 활발해지고 있으며, 메모리 모듈 또한 대용화가 이루어지고 있다. 이에 대용량 메모리를 64비트 CPU 플랫폼에서 효과적으로 테스트하는 방법을 개발할 필요성이 대두되고 있다. 본 논문에서는 x86-64 기반 리눅스 2.6.11 커널에서 물리 메모리의 테스트 영역을 확장하는 기법을 제안한다. 제안된 기법에는 응용이나 커널에서 물리 메모리에 대한 직접 접근, 프로그램을 사용자가 원하는 물리 메모리로 배치, 프로그램의 동적 재배치 등의 방법을 통해 테스트 영역을 확장 한다. 현재 64 비트 CPU를 지원하는 OS는 리눅스와 윈도우즈 64비트 에디션 등이 있다. 기존 리눅스 커널을 그대로 사용하였을 때 프로그램 등이 이미 사용 중인 물리 메모리에 대해서는 메모리 테스트를 수행 할 수 없었으나, 각 프로그램들을 물리 메모리에서 재배치하여, 원하는 곳의 메모리를 테스트 할 수 있도록 커널 수정을 통하여 구현하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.69-81
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• 2008

The density of Memory has been increased by great challenge for memory technology, so elements of memory become smaller than before and the sensitivity to faults increases. As a result of these changes, memory testing becomes more complex. The number of storage elements is increased per chip, and the cost of test becomes more remarkable as the cost per transistor drops. Proposed design doesn't need to control from outside environment, because it integrates into memory. The proposed scheme supports the various memory testing algorithms. Consequently, the proposed one is more efficient in terms of test cost and test data to be applied. Moreover, we proposed a reallocation algorithm for faulty memory parts. It has an efficient reallocation scheme with row and column redundant memory. Previous reallocation information is obtained from faulty memory every each tests. However proposed scheme avoids to this problem. because onetime test result from reallocation information can save to flash memory. In this paper, a reallocation scheme has been increased efficiency because of using flash memory.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.72-79
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• 2003

Due to the improvements in circuit design technique and manufacturing technique, complexity of a circuit is growing along with the demand for memories with large capacities. Likewise, as a memory capacity gets larger, testing gets harder and testing cost increases, and testing process in chip development gets larger as well. Therefore, a research on an effective test algorithm to improve the chip yield rate in a short time period is becoming an important task. This paper proposes an effective, March C-algorithm based, test algorithm that can also be applied to a dual-port memory since it considers all the fault types, which can be occurred in a single-port as well as in a dual-port memory, without increasing the test length.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04b
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• pp.1631-1634
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• 2002

본 논문에서는 PC상에서 내장 메모리를 테스트 할 수 있는 테스트 시스템을 구현하였다. 테스트상으로는 Synchronous DRAM을 사용하였고 내장 자체 테스트 회로에 10N March C 알고리즘을 적용, DSRAM, SRAM을 제어하는 테스트 시스템 제어기를 설계하였다. 본 테스트 시스템은 메모리 테스트 검증을 고가의 테스트 장비 없이 용이하게 하도록 설계되었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.72-85
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• 2007

The development of memory design and process technology enabled the production of high density memory. However, this increased the complexity of the memory making memory testing more complicated, and as a result, it brought about an increase in memory testing costs. Effective memory test algorithm must detect various types of defects within a short testing time, and especially in the case of port memory test algorithm, it must be able to detect single port memory defects, and all the defects in the dual port memory. The March A2PF algorithm proposed in this paper is an effective test algorithm that detects all types of defects relating to the duel port and single port memory through the short 18N test pattern.

• Journal of KIISE:Computing Practices and Letters
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• v.7 no.1
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• pp.99-107
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• 2001

In this paper, we implemented memory BIST circuit based on ION march algorithm, and the IEEE 1149.1 has been designed as main controlJer for embedded memory testing. The implemented memory BIST can be used for word-oriented memory since it adopts background data, this is avaliable for word-oriented memory. It is able to detect all stuck-at faults, transition faults, coupling faults, and address decoder faults in the word-oriented memory. Memory BIST and IEEE 1149.1 are described at RTL level in Verilog-HDL, and synthesized with the Synopsys. The synthesized circuits are fully velified using VerilogXL and memory cell generated by memory compiler.

• Journal of KIISE:Software and Applications
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• v.34 no.8
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• pp.708-720
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• 2007

Memory access errors are frequently occurred in computer programs written in C programming language [1,2]. Accordingly, a number of research works have suggested a wide variety of methods to detect such errors automatically. However, they have one or more of the following problems: inability to detect all memory errors, changing the memory allocation mechanism, and excessive performance overhead. To cope with these problems, in this paper we suggest a new and automated tool to detect dynamic memory access errors in C programs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.61-70
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• 2007

The density of Memory has been increased by great challenge for memory technology. Therefore, elements of memory become more smaller than before and the sensitivity to faults increases. As a result of these changes, memory testing becomes more complex. In addition, as the number of storage elements per chip increases, the test cost becomes more remarkable as the cost per transistor drops. Recent development in system-on-chip (SOC) technology makes it possible to incorporate large embedded memories into a chip. However, it also complicates the test process, since usually the embedded memories cannot be controlled from the external environment. Proposed design doesn't need controls from outside environment, because it integrates into memory. In general, there are a variety of memory modules in SOC, and it is not possible to test all of them with a single algorithm. Thus, the proposed scheme supports the various memory testing process. Moreover, it is able to At-Speed test in a memory module. consequently, the proposed is more efficient in terms of test cost and test data to be applied.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.11B
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• pp.1957-1965
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• 2000

본 논문에서는 휴대 멀티미디어 응용을 위한 MDSP(Multimedia Fixed Point DSP) 칩의 내장 메모리 테스트와 기판 수준의 테스트를 지원하기 위해 내장 메모리 테스트를 위한 자체 테스트 기법, 기판 수준의 테스트 지원 및 내장 메모리를 위한 자체 테스트 회로를 제어하기 위한 경계 주사 기법을 구현하였다. 본 논문에서 구현한 기법들은 Verilog HDL을 이용하여 회로들을 설계하였으며, Synopsys 툴과 현대 heb60 라이브러리를 이용하여 합성하였다. 그리고 회로 검증을 위한 시뮬레이터는 Cadence사의 VerilogXL을 사용하였다.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.3
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• pp.209-216
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• 2011

Recently the design of SoCs(System-on-Chips) in which TCM is embedded for high speed operation increases rapidly. In this paper, a parallel test structure for eDRAM-based TCM embedded in SoCs is proposed. In the presented technique, the MUT (Memory Under Test) is changed to parallel structure and it increases testability of MUT with boundary scan chains. The eDRAM is designed in structure for parallel test so that it can be tested for each modules. Dynamic test can be performed based on input-output data. The proposed techniques are verified their performance by circuits simulation.