Programmable Memory BIST and BISR Using Flash Memory for Embedded Memory

내장 메모리를 위한 프로그램 가능한 자체 테스트와 플래시 메모리를 이용한 자가 복구 기술

  • 홍원기 (숭실대학교 컴퓨터학과) ;
  • 최정대 (숭실대학교 컴퓨터학과) ;
  • 심은성 (숭실대학교 컴퓨터학과) ;
  • 장훈 (숭실대학교 컴퓨터학과)
  • Published : 2008.02.25

Abstract

The density of Memory has been increased by great challenge for memory technology, so elements of memory become smaller than before and the sensitivity to faults increases. As a result of these changes, memory testing becomes more complex. The number of storage elements is increased per chip, and the cost of test becomes more remarkable as the cost per transistor drops. Proposed design doesn't need to control from outside environment, because it integrates into memory. The proposed scheme supports the various memory testing algorithms. Consequently, the proposed one is more efficient in terms of test cost and test data to be applied. Moreover, we proposed a reallocation algorithm for faulty memory parts. It has an efficient reallocation scheme with row and column redundant memory. Previous reallocation information is obtained from faulty memory every each tests. However proposed scheme avoids to this problem. because onetime test result from reallocation information can save to flash memory. In this paper, a reallocation scheme has been increased efficiency because of using flash memory.

메모리 기술이 발달함에 따라 메모리의 집적도가 증가하게 되었고, 이러한 변화는 구성요소들의 크기를 작아지게 만들고, 고장의 감응성이 증가하게 하였다. 그리고 고장은 더욱 복잡하게 되었다. 또한, 칩 하나에 포함되어있는 저장 요소가 늘어남에 따라 테스트 시간도 증가하게 되었다. 본 논문에서 제안하는 테스트 구조는 내장 테스트를 사용하여 외부 테스트 환경 없이 테스트가 가능하다. 제안하는 내장 테스트 구조는 여러 알고리즘을 적용 가능하므로 높은 효율성을 가진다. 또한 고장 난 메모리를 여분의 메모리로 재배치함으로써 메모리 수율 향상과 사용자에게 메모리를 투명하게 사용할 수 있도록 제공할 수 있다. 본 논문에서는 고장 난 메모리 부분을 여분의 행과 열 메모리로 효율적인 재배치가 가능한 복구 기술을 포함한다. 재배치 정보는 고장 난 메모리를 매번 테스트 해야만 얻을 수 있다. 매번 테스트를 통해 재배치 정보를 얻는 것은 시간적 문제가 발생한다. 이것을 막기 위해 한번 테스트해서 얻은 재배치 정보를 플래시 메모리에 저장해 해결할 수 있다. 본 논문에서는 플래시 메모리를 이용해 재배치 정보의 활용도를 높인다.

Keywords

References

  1. A. J. van de Goor and A. Offerman, "Towards a uniform notation for memory tests," in Proc. European Design and Test Conf., pp. 420-427, 1996
  2. V. G. Mikitjuk, V. N. Yarmolik and A. J. van de Goor, "RAM testing algorithms for detecting multiple linked faults," in Proc. European Design and Test Conf., pp. 435-439, 1996
  3. P. H. Bardell and W. H. McAnney, "Built-in test for RAMs," IEEE Design & Test of Computers, Vol. 5, No. 4, pp. 29-36, Aug 1988 https://doi.org/10.1109/54.7967
  4. V. D. Agrawal, C. R. Kime and K. K. Saluja, "A tutorial on built-in self-test. I. Principles," IEEE Design & Test of Computers, Vol. 10, No. 1, pp. 73-82, Mar 1993 https://doi.org/10.1109/54.199807
  5. V. D. Agrawal, C. R. Kime and K. K. Saluja, "A tutorial on built-in self-test. 2. Principles," IEEE Design & Test of Computers, Vol. 10, No. 2, pp. 69-77, Mar 1993 https://doi.org/10.1109/54.211530
  6. S. Park, K. Lee, C. Im, N. Kwak, K. Kim and Y. Choi, "Designing built-in self-test circuits for embedded memories test," in Proc. AP-ASIC 2000, 2nd IEEE Asia Pacific Conf., pp. 315-318, Aug 2000
  7. K. Zarrineh and S. J. Upadhyaya, "On programmable memory built-in self test architectures," in Proc. IEEE Design, Automation and Test in Europe Conf., pp. 708-713, Mar 1999
  8. Horiguchi M., Etoh J., Aoki M., Itoh K., and Matsumoto T., "A flexible redundancy technique for high-density DRAMs," IEEE Journal of Solid-State Circuits, vol. 26, pp. 12-17, January 1991 https://doi.org/10.1109/4.65704
  9. Ilyoung Kim, Zorian Y., Komoriya G., Pham H., Higgins F.P., and Lewandowski J.L., "Built in self repair for embedded high density SRAM," Proceedings of International Test Conference, pp. 1112-1119, 18-23 October 1998
  10. Heon Cheol Kim, Dong Soon Yi, Jin Young Park, and Chang Hyun Cho, "A BISR (built-in self-repair) circuit for embedded memory with multiple redundancies," International Conference on VLSI and CAD, pp. 602-605, 26-27 October 1999
  11. Sy Yen Kuo, and Fuchs W.K., "Efficient Spare Allocation in Reconfigurable Arrays" Conference on Design Automation, pp. 385-390, 29-2 June 1986
  12. Chin Long Wey, and Lombardi F., "On the Repair of Redundant RAM's," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 6, pp. 222-231, March 1987 https://doi.org/10.1109/TCAD.1987.1270266
  13. Wei Kang Huang, Yi Nan Shen, and Lombardi F., "New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement," IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, vol. 9, pp. 323-328, March 1990 https://doi.org/10.1109/43.46807
  14. V. Schober, S. Paul, and O. Picot, "Memory Built-In Self-Repairusingredundant words", Proceedings of International Test Conference, 2001
  15. R. Dean Adams, "High Performance Memory Testing: Design Principles, Fault Modeling and Self-Test", Kluwer Academic Publishers, 2003
  16. S. Hamdioui, G. Gaydadjiev and A. J. van de Goor, "The state-of-art and future trends in testing embedded memories," Memory Technology, Design and Testing, 2004. Records of the 2004 International Workshop, pp. 54-59, Aug 2004
  17. S. Hamdioui, A. J. van de Goor and M. Rodgers, "March SS: A Test for All Static Simple RAM Faults," Memory Technology, Design and Testing, 2002. (MTDT 2002). in Proc. The 2002 IEEE International Workshop, pp. 95-100, July 2002
  18. P. C. Tsai, S. J. Wang and F. M. Chang, "FSM-Based Programmable Memory BIST with Macro Command," in Proc. The 2005 IEEE International Workshop on Memory Technology, Design, and Testing, pp. 72-75, Aug 2005