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An Efficient Test Algorithm for Dual Port Memory  

김지혜 (연세대학교 전기전자공학과)
송동섭 (연세대학교 전기전자공학과)
배상민 (삼성전자 CAE 센터)
강성호 (연세대학교 전기전자공학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.40, no.1, 2003 , pp. 72-79 More about this Journal
Abstract
Due to the improvements in circuit design technique and manufacturing technique, complexity of a circuit is growing along with the demand for memories with large capacities. Likewise, as a memory capacity gets larger, testing gets harder and testing cost increases, and testing process in chip development gets larger as well. Therefore, a research on an effective test algorithm to improve the chip yield rate in a short time period is becoming an important task. This paper proposes an effective, March C-algorithm based, test algorithm that can also be applied to a dual-port memory since it considers all the fault types, which can be occurred in a single-port as well as in a dual-port memory, without increasing the test length.
Keywords
이중포트메모리;테스트;고장모델;
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