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Programmable Memory BIST and BISR Using Flash Memory for Embedded Memory  

Hong, Won-Gi (Department of Computer, Soongsil University)
Choi, Jung-Dai (Department of Computer, Soongsil University)
Shim, Eun-Sung (Department of Computer, Soongsil University)
Chang, Hoon (Department of Computer, Soongsil University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.45, no.2, 2008 , pp. 69-81 More about this Journal
Abstract
The density of Memory has been increased by great challenge for memory technology, so elements of memory become smaller than before and the sensitivity to faults increases. As a result of these changes, memory testing becomes more complex. The number of storage elements is increased per chip, and the cost of test becomes more remarkable as the cost per transistor drops. Proposed design doesn't need to control from outside environment, because it integrates into memory. The proposed scheme supports the various memory testing algorithms. Consequently, the proposed one is more efficient in terms of test cost and test data to be applied. Moreover, we proposed a reallocation algorithm for faulty memory parts. It has an efficient reallocation scheme with row and column redundant memory. Previous reallocation information is obtained from faulty memory every each tests. However proposed scheme avoids to this problem. because onetime test result from reallocation information can save to flash memory. In this paper, a reallocation scheme has been increased efficiency because of using flash memory.
Keywords
Embedded Memory; BIST; Programmable BIST; BISR;
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  • Reference
1 A. J. van de Goor and A. Offerman, "Towards a uniform notation for memory tests," in Proc. European Design and Test Conf., pp. 420-427, 1996
2 Heon Cheol Kim, Dong Soon Yi, Jin Young Park, and Chang Hyun Cho, "A BISR (built-in self-repair) circuit for embedded memory with multiple redundancies," International Conference on VLSI and CAD, pp. 602-605, 26-27 October 1999
3 S. Park, K. Lee, C. Im, N. Kwak, K. Kim and Y. Choi, "Designing built-in self-test circuits for embedded memories test," in Proc. AP-ASIC 2000, 2nd IEEE Asia Pacific Conf., pp. 315-318, Aug 2000
4 V. G. Mikitjuk, V. N. Yarmolik and A. J. van de Goor, "RAM testing algorithms for detecting multiple linked faults," in Proc. European Design and Test Conf., pp. 435-439, 1996
5 V. D. Agrawal, C. R. Kime and K. K. Saluja, "A tutorial on built-in self-test. I. Principles," IEEE Design & Test of Computers, Vol. 10, No. 1, pp. 73-82, Mar 1993   DOI   ScienceOn
6 K. Zarrineh and S. J. Upadhyaya, "On programmable memory built-in self test architectures," in Proc. IEEE Design, Automation and Test in Europe Conf., pp. 708-713, Mar 1999
7 S. Hamdioui, G. Gaydadjiev and A. J. van de Goor, "The state-of-art and future trends in testing embedded memories," Memory Technology, Design and Testing, 2004. Records of the 2004 International Workshop, pp. 54-59, Aug 2004
8 Ilyoung Kim, Zorian Y., Komoriya G., Pham H., Higgins F.P., and Lewandowski J.L., "Built in self repair for embedded high density SRAM," Proceedings of International Test Conference, pp. 1112-1119, 18-23 October 1998
9 Chin Long Wey, and Lombardi F., "On the Repair of Redundant RAM's," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 6, pp. 222-231, March 1987   DOI   ScienceOn
10 Sy Yen Kuo, and Fuchs W.K., "Efficient Spare Allocation in Reconfigurable Arrays" Conference on Design Automation, pp. 385-390, 29-2 June 1986
11 R. Dean Adams, "High Performance Memory Testing: Design Principles, Fault Modeling and Self-Test", Kluwer Academic Publishers, 2003
12 V. D. Agrawal, C. R. Kime and K. K. Saluja, "A tutorial on built-in self-test. 2. Principles," IEEE Design & Test of Computers, Vol. 10, No. 2, pp. 69-77, Mar 1993   DOI   ScienceOn
13 Wei Kang Huang, Yi Nan Shen, and Lombardi F., "New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement," IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, vol. 9, pp. 323-328, March 1990   DOI   ScienceOn
14 Horiguchi M., Etoh J., Aoki M., Itoh K., and Matsumoto T., "A flexible redundancy technique for high-density DRAMs," IEEE Journal of Solid-State Circuits, vol. 26, pp. 12-17, January 1991   DOI   ScienceOn
15 P. H. Bardell and W. H. McAnney, "Built-in test for RAMs," IEEE Design & Test of Computers, Vol. 5, No. 4, pp. 29-36, Aug 1988   DOI   ScienceOn
16 S. Hamdioui, A. J. van de Goor and M. Rodgers, "March SS: A Test for All Static Simple RAM Faults," Memory Technology, Design and Testing, 2002. (MTDT 2002). in Proc. The 2002 IEEE International Workshop, pp. 95-100, July 2002
17 P. C. Tsai, S. J. Wang and F. M. Chang, "FSM-Based Programmable Memory BIST with Macro Command," in Proc. The 2005 IEEE International Workshop on Memory Technology, Design, and Testing, pp. 72-75, Aug 2005
18 V. Schober, S. Paul, and O. Picot, "Memory Built-In Self-Repairusingredundant words", Proceedings of International Test Conference, 2001