• The Transactions of the Korea Information Processing Society
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• v.6 no.2
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• pp.497-511
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• 1999

Recently, many parallel processing technologies were developed, ILP(Instruction level Parallelism) processor's performance have been growed very rapidly. especially, EPIC(Explicitly Parallel Instruction computing) architectures attempt to enhance the performance in the predicated execution and speculative execution with the hardware. In this paper to improve the code scheduling possibility by applying to the characteristics of EPIC architectures, a new register allocation algorithm is proposed. And we proves that proposed register allocation algorithm is more efficient scheme than the conventional scheme when predicated execution is applied to our scheme by experiments. In experimental results, it shows much more performance enhancement, about 19% in proposed scheme than the conventional scheme. So, our scheme is verified that it is an effective register allocation method.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.17-29
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• 1999

This paper presents a high level synthesis method targeting low power consumption for data-dominated CMOS circuits (e.g., DSP). The high level synthesis is divided into three basic tasks: scheduling, resource and register allocation. For lower power scheduling, we increase the possibility of reusing an input operand of functional units. For a scheduled data flow graph, a compatibility graph for register and resource allocation is formed, and then a special weighted network is then constructed from the compatibility graph and the minimum cost flow algorithm is performed on the network to obtain the minimum power consumption data path assignment. The formulated problem is then solved optimally in polynomial time. This method reduces both the switching activity and the capacitance in synthesized data path. Experimental results show 15% power reduction in benchmark circuits.

• Electronics and Telecommunications Trends
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• v.5 no.2
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• pp.156-169
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• 1990

본 기술동향에서는 시스템에서 요구되는 동작에 관한 기술을 레지스터 전송 수준의 구조에 관한 기술로 바꾸는 상위 수준 합성에 대하여 그 현황을 분석하였다. 현황 분석은 스케줄링과 할당으로 나누어 진행하였으며, 상위 수준 합성의 필요성, 내용, 기법 분석 및 시스템 분석을 행하였다. 현재의 연구가 갖는 문제점을 검토하였으며, 앞으로의 전망을 예측하였다.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.2
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• pp.200-208
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• 2000

Multi-ports register could shared several instructions at the same time in read operation. We address a formal methods for describing timing analysis and resource restriction in pipeline super scalar process that having multi-Port registers. First, we specify in-order pipeline instructions, and then, extend timing analysis in out-of-order super-scalar. In this case, we find instruction pairs in any cycle which can execute same time, We use ACSR(Algebra of Communicating Shared Resources), a branch of formal methods based on process algebra, for instruction specification and modelling.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.329-334
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• 2002

For the testability, this paper proposed the algorithm at autonomous synthesis which includes the data path structure as the self testing as possible on high level synthesis method when VHDL, coding is used in the system design area. In the proposed algorithm of this paper, MUXs and registers are assigned to the data path of designed system. And the designed data path could be mapped the H/W specification of described VHDL coding to the testable library. As a results, it was mapped H/W to the assign algorithm that is minimized MUX and the registers in collision graph.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.555-562
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• 2008

In this paper we proposed a practical low-power design technique using clock-gating in RTL. An efficient low-power methodology is that a high-level designer analyzes a generic system and designs a controller for clock-gating. Also the desirable flow is to derive clock-gating in normal synthesis process by synthesis tool than to insert directly gate to clock line. If low-power is considered in coding process, clock is gated in coding process. If not considered, after analyzing entire operation. clock is Bated in periods of holding data. After analyzing operation for clock-gating, a controller was designed for it, and then a low-power circuit was generated by synthesis tool. From result, we identified that the consumed power of register decreased from 922mW to 543mW, that is the decrease rate is 42%. In case of synthesizing the test circuit using synthesizer of Power Theater, it decreased from 322mW to 208mW (36.5% decrease).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.66-66
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• 2001

새로운 마이크로프로세서의 설계, 최적화, 그리고 완성 후 어플리케이션의 작성 단계에서 칩의 명령어 집합 시뮬레이션은 필수적인 요소이다. 그러나, 기존의 시뮬레이션 툴들은 저 수준의 하드웨어 기술언어와 게이트 레벨 이하의 시뮬레이션으로 인해 시뮬레이터 구성과 실행 시에 상당한 시간적 지연을 초래하고 있다. 본 논문에서는 이러한 문제들을 해소하고 칩 제작과정에서 발생하는 잦은 설계 변경에 유연성 있게 대응할 수 있는 레지스터 전송 수준의 명령어 집합 시뮬레이터 생성기를 제안하며 그 설계 및 구현에 관해 기술한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.2
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• pp.55-65
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• 2004

In this paper, An efficient non-scan DFT method for datapaths described in RTL is proposed. The proposed non-scan DFT method improves testability of datapaths based on hierarchical testability analysis regardless to width of the datapath. It always guarantees higher fault efficiency and faster test pattern generation time with little hardware overhead than previous methods. The experimental result shows the superiority of the proposed method of test pattern generation time, application time, and area overhead compared to the scan method.

• The Transactions of the Korea Information Processing Society
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• v.7 no.2
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• pp.470-476
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• 2000

This paper describes an IP design of a low-power microcontroller using an architecture level design methodology instead of a transistor level. To reduce switching capacitance, the register-toregister data transfer is adopted to frequently used register transfer micro-operations. Also, distributed buffers are proposed to reduce a input data rising edge time. To reduce power consumption without any loss of performance, pipeline processing should be used. In this paper, a 4-stage pipelined datapath being able to process CISC instructions is designed. Designed microcontroller lessens power consumption by 20%. To measure a power consumption, the SYNOPSYS EPIC powermill is used.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.757-759
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• 2013

Until just a few years ago, digital circuit design techniques in register transfer level using Verilog or VHDL have been recognized as the up-to-date way compared with the traditional schematic design, and truly they have been used as the most popular skill for most chip designs. However, with the advent of era in which the complexity of semiconductor chip counts over billion transistors with advanced manufacturing technology, designing in register transfer level became too complex to meet the requirements of the needs, so the design paradigm has to change so that both design and synthesis can be done in higher level of abstraction. Bluespec SystemVerilog (BSV) is the only HDL which enables both circuit design and generating synthesizable code in the system level developed so far. In this contribution, I survey and analyze the features which supports the new paradigm in the BSV HDL, not very familiar to industry yet.