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http://dx.doi.org/10.6109/jkiice.2008.12.3.555

Gated Clock-based Low-Power Technique based on RTL Synthesis  

Seo, Young-Ho (광운대학교 교양학부 IT)
Park, Sung-Ho (LG 전자 SIC 사업팀 HPM Gr)
Choi, Hyun-Joon (광운대학교 전자재료공학과 Digital Design & Test Lab.)
Kim, Dong-Wook (광운대학교 전자재료공학과 Digital Design & Test Lab.)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.12, no.3, 2008 , pp. 555-562 More about this Journal
Abstract
In this paper we proposed a practical low-power design technique using clock-gating in RTL. An efficient low-power methodology is that a high-level designer analyzes a generic system and designs a controller for clock-gating. Also the desirable flow is to derive clock-gating in normal synthesis process by synthesis tool than to insert directly gate to clock line. If low-power is considered in coding process, clock is gated in coding process. If not considered, after analyzing entire operation. clock is Bated in periods of holding data. After analyzing operation for clock-gating, a controller was designed for it, and then a low-power circuit was generated by synthesis tool. From result, we identified that the consumed power of register decreased from 922mW to 543mW, that is the decrease rate is 42%. In case of synthesizing the test circuit using synthesizer of Power Theater, it decreased from 322mW to 208mW (36.5% decrease).
Keywords
low-power; power estimation; RTL; synthesis; ASIC; VLSI;
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