• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.283-284
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• 2015

일반적인 LLC 공진형 컨버터의 경우, 경 부하 시의 레귤레이션이 안 되는 문제가 존재한다. 본 논문에서는 경 부하 시 레귤레이션이 안 되는 문제점에 대하여 보드 선도를 이용하여 직관적인 해석을 유도한다. 또한 이러한 문제점을 개선하기 위한 방법을 제안하고, 이를 보드 선도를 이용하여 특성을 분석한다. 이를 통하여 일반적인 LLC 공진형 컨버터의 특성을 유지하면서, 경 부하 시의 레귤레이션 문제를 해결한다.

• 전자공학회논문지 IE
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• v.48 no.4
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• pp.13-18
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• 2011

In this paper, we have examined electrical characteristics of LDO regulator according to the process variation using a 1 ${\mu}m$ 20 V high voltage CMOS process. The electrical analysis of LDO regulator have been performed with three kind of SPICE parameter sets (Typ : typical, FF : fast, SS : slow) by process variation which cause change of SPICE parameter such as threshold voltage and effective channel length of MOS devices. From simulation results, we confirmed that in case of SS type SPICE parameter set, the LDO regulator has 3.6 mV/V line regulation, 0.4 mV/mA load regulation and 0.86 ${\mu}s$ output voltage settling time. And in case of Typ type SPICE parameter set, the LDO regulatorhas 4.2 mV/V line regulation, 0.44 mV/mA load regulation and 0.62 ${\mu}s$ output voltage settling time. Finally, in the FF type SPICE parameter set, the LDO regulator has 7.0 mV/V line regulation, 0.56 mV/mA load regulation and 0.27 ${\mu}s$ output voltage settling time.

• Journal of IKEEE
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• v.26 no.3
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• pp.462-467
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• 2022

The feedback buffer structure is proposed to alleviate the overshoot and undershoot phenomenon and the regulation of the output voltage. The conventional LDO regulator undergoes a regulation voltage change caused by a constant load current change. An LDO regulator with a feedback voltage sensing structure operates in the input voltage range of 3.3 to 4.5 V and has a load current of up to 150 mA at output voltage of 3 V. According to the simulation results, a regulation value of 6.2 mV was ensured when the load current uniformly changed to 150 mA.

• Journal of IKEEE
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• v.27 no.3
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• pp.308-312
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• 2023

The gate current sensing structure was proposed to more effectively control the regulation of the output voltage when the LDO regulator occurs in an overshoot or undershoot situation. In a typical existing LDO regulator, the regulation voltage changes when the load current changes. However, the operation speed of the pass transistor can be further improved by supplying/discharging the gate terminal current in the pass transistor using a gate current sensing structure. The input voltage of the LDO regulator using the gate current sensing structure is 3.3 V to 4.5 V, the output voltage is 3 V, and the load current has a maximum value of 250 mA. As a result of the simulation, a voltage change value of about 12 mV was confirmed when the load current changed up to 250 mA.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.165-166
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• 2014

기존 LED(Light Emitting Diode) 전류 제어용 SSPR(Secondary Side Post Regulator) 스위치를 갖는 구조의 다중출력 컨버터는 LED 정 전류 제어를 위한 별도의 부스트 컨버터 없이 전류제어가 가능하여 원가 및 부피 저감과 효율이 상승하는 장점이 있다. 하지만, 주 출력단(Master)의 피드백을 받아 1차 측 메인 스위치를 제어하게 되어 제어 회로가 복잡하고 주 출력단 부하 변동에 의해 부 출력단(Slave)의 크로스-레귤레이션(Cross-Regulation) 특성이 좋지 않은 단점이 있다. 따라서, 본 논문에서는 기존 SSPR 스위치의 장점을 갖고 주 출력 단의 부하 변동에도 부 출력단의 크로스-레귤레이션 특성이 좋은 새로운 직렬 공진형 LED 구동회로를 제안한다. 최종적으로 제안 회로를 4채널 LED 구동회로에 적용하여 그 실험결과를 바탕으로 제안 회로의 타당성을 검증하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.7
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• pp.993-1000
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• 2018

This paper proposes a low-dropout voltage regulator(LDO) using self-cascode structure. The self-cascode structure was optimized by adjusting the channel length of the source-side MOSFET and applying a forward voltage to the body of the drain-side MOSFET. The self-cascode of the input differential stage of the error amplifier is optimized to give higher transconductance, but the self-cascode of the output stage is optimized to give higher output resistance, The proposed LDO using self-cascode structure was designed by a $0.18{\mu}m$ CMOS technology and simulated using SPECTRE. The load regulation of the proposed LDO regulator was 0.03V/A, whereas that of the conventional LDO was 0.29V/A. The line regulation of the proposed LDO regulator was 2.23mV/V, which is approximately three times improvement compared to that of the conventional LDO. The transient response of the proposed LDO regulator was 625ns, which is 346ns faster than that of the conventional LDO.

• Proceedings of the KIPE Conference
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• 2013.11a
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• pp.194-195
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• 2013

본 논문에서는 다출력 SMPS의 출력전압 레귤레이션을 개선하기 위한 post regulation 기법들에 대해 분석한다. 그리고 출력전압 레귤레이션을 위한 기법인 built-in 컨버터에 대해 제안하고, 그 특성에 대해 분석한다. 이를 토대로 시뮬레이션을 구성하여 다른 post regulation 기법들을 적용한 결과와 본 논문에서 제안한 built-in 컨버터를 적용한 결과를 비교/분석하여 제안한 기법의 타당성을 검증한다.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.6
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• pp.539-546
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• 1999

A new integrated single-stage zero current switched(ZCS) quasi resonant convertedQRC) for the IX)wer f factor correction(PFCl converter is introduced in this paper. The power factor correction can be achieved by t the discontinuous conduction mod$\varepsilon$(DCM) operation of an input current. The proposed converter has the c characteristics of the good IX)wer factor, 10씨 line current harmonics, and tight output regulation. Furthern10re, t the ringing effect due to the output capacitance of the main switch can be eliminated by use of‘ active clamp c circuit. Therefore, the proIX)sed converter is expecttc'(] to be suitable for a compact power converter with a t tightly regulated output voltage requiring a switching frequency of more than several hundrtc'(]s kHz.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.4
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• pp.1222-1228
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• 2010

This paper presents a design of the CMOS LDO regulator with a fast transient response for a high speed PMIC(power management integrated circuit). Proposed LDO regulator circuit consists of a reference voltage circuit, an error amplifier and a power transistor. 2-stage wide-band OTA buffer between error amplifier and power transistor is added for a good output stability. Although conventional source follower buffer structure is simple, it has a narrow output swing and a low S/N ratio. In this paper, we use a 2-stage wide-band OTA instead of source follower structure for a buffer. From HSPICE simulation results using a $0.5{\mu}m$ CMOS standard technology, simulation results were 16 mV/V line regulation and 0.007 %/mA load regulation.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.60 no.3
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• pp.126-132
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• 2011

A conventional LDO(Low Dropout Regulator) uses one OPAMP and one signal path. This means that OPAMP's DC Gain and Bandwidth can't optimize simultaneously within usable power. This also appears that regulation property and settling time of LDO can't improve at the same time. Based on this idea, a proposed LDO uses two OPAMP and has two signal path. To improve regulation property, OPAMP where is used in the path which qualities DC gain on a large scale, bandwidth designed narrowly. To improve settling time, OPAMP where is used in the path which qualities DC gain small, bandwidth designed widely. A designed LDO used 0.5um 1P2M process and provided 200mA of output current. A line regulation and load regulation is 12.6mV/V, 0.25mV/mA, respectively. And measured settling time is 1.5us in 5V supply voltage.