• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1197-1200
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• 2003

This paper presents A/D converter for the signal processing of infrared sensor and CMOS image sensor. The A/D converter designed in a 0.25um CMOS process provides a resolution of 10bits at a sampling rate of 50MS/s while dissipating 67mW at 2.5V supply voltage. This A/D converter is based on a pipeline architecture in which the number of bits converted per stage and the stage number are optimized to achieve the desired linearity and reduce power consumption as well. Simulation results show that the A/D converter using 1.5bit per stage MDAC with switched capacitors and dynamic comparators efficiently reduces the power consumption.

• Transactions of the Korean Society of Mechanical Engineers
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• v.19 no.3
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• pp.680-687
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• 1995

In recent years, grinding techniques for precision machining of brittle materials used in electric, optical and magnetic parts have been improved by using superabrasive wheel and precision grinding machine. The completion of optimum dressing of superabrasive wheel makes possible the effective precision grinding of brittle materials. But the present dressing system cannot have control of optimum dressing of the superabrasive wheel. This study has proposed a new optimum in-process electrolytic dressing system. This system can carry out optimum in-process dressing of superabrasive wheel, and give very effective control according to gap increase.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.253-256
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• 2001

This paper introduces the design of high-speed analog- to-digital converter for high-definition TV, camcorders, portable equipments and implemented in a 0.65${\mu}{\textrm}{m}$ CMOS technology. Key circuits developed for low power and high speed A/D converter are a dynamic comparator that consumes no static power, a source follower buffered op amp that achives wide bandwidth using large input devices. The converter achieves low power dissipation of 40-mW at 3.3-V power supply. Measured performance includes 0.53 LSB of INL and 0.48 LSB of DNL while sampling at 60MHz.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.255-258
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• 1999

This paper describes a 40-Msample/s 10-bit CMOS folding and interpolating analog-to-digital converter (ADC). A new 2-step architecture is proposed. The proposed architecture is composed of a coarse ADC bloch for the 6bits of MSBs and a fine ADC block for the remaining 4bits. The amplified folding analog signals in the coarse ADC are selectively chosen for the fine ADC. In the fine ADC, the bubble errors of the comparators are corrected by using the BGM(binary-gray-mixed) code[1] and extra two comparators are used to correct underflow and overflow errors. The proposed ADC was simulated using CMOS 0.25${\mu}{\textrm}{m}$ parameters and occupies 1.0mm$\times$1.0mm. The power consumption is 48㎽ at 40MS/s with 2.5-V power supply. The INL is under $\pm$2.0LSB and the DNL. is under $\pm$1.0LSB by Matlab simulations.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.2
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• pp.295-301
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• 2012

In this article, we have designed SHA, which has 12 Bit resolution at an input signal range of 1 $V_{pp}$ and operates at a sampling speed of 100 MS/s in order to use at front of high speed ADC. SFDR(Spurious Free Dynamic Range) of the proposed system drops to approximately 66.3 dB resolution when the input frequency is 5 MHz, and the sampling frequency is 100 MHz, however, the circuit without a feedthrough has 12 bit resolution with approximately 73 dB.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.609-612
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• 2002

In this paper, a 12-bit 100-MHz CMOS current steering digital-to-analog converter is designed. In the D/A converter, a driver circuit using a dynamic latch is implemented to obtain low glitch and thermometer decoder is used for low DNL errors, guaranteed monotonicity, reduced stitching noise. And a threshold voltage-compensated current source. The D/A converter is designed with 0.35-$\mu m$ CMOS technology at 3.3 V power supply and simulated with HSPICE. The maximum power dissipation of the designed DAC is 143 mW.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.325-329
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• 2011

This paper introduces the 10b 1MS/s SAR ADC with double sampling technique to reduce the power consumption. The SAR ADC is implemented in CMOS 1P8M 65nm technology and occupies 0.11um2. The maximum sampling rate is 1MS/s. The simulated SNDR and SFDR are 55.6dB and 62.7dB at 484kHz input frequency, respectively. The implemented data converter consumes 507uW with 1.2-V supply.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.950-953
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• 2003

In this paper, sigma-delta A/D converter for ADSL modems using oversampling technique is designed. Conventionally, the oversampling A/D converter is consist of opamps, switched capacitors, quantizers, infernal D/A converters, and decimation filters. 3-bit flash A/D converter, 3-bit thermometer-based D/A converters, and sub-blocks are used for high speed operation. HSPICE simulator and CADENCE tool are used for verification and layout of the designed modulator. The internal A/D converter and D/A converters are operated at 130 MHz. In design of decimation filter Matlab is used for calculating coefficients and ModelSim and VHDL are used for design.

• Proceedings of the Korea Information Processing Society Conference
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• 2004.05a
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• pp.797-800
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• 2004

FED(Field Emission Display)는 CRT(Cathode Ray Tube)의 화질과 LCD(Liquid Crystal Display)와 같은 FPD(Flat Panel Display)의 경량, 박형의 장점을 만족시키는 차세대 Display 소자로서 주목을 받고 있다. 본 논문은 저항열을 이용하여 256 Gray-Scale Level을 출력하는 8 비트 FED Data Driver IC 설계에 관한 것이다. 즉, 저항열과 D/A 변환기를 통하여 디지털 입력 데이터에 따른 아날로그 출력 데이터를 갖는 FED 용 Data Driver IC이다. 본 논문에서 설계된 Driver IC는 집적도를 높여 Output Channel 수를 증가시키는 것을 목표로, 하이닉스 0.6um High Voltage 공정을 사용하였으며, 8 비트 RGB 데이터 입력과 40V 구동전압에서 동작하도록 설계하였다.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.752-755
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• 2004

본 논문에서는 전력변환회로의 소신호 모델을 이용한 데드빗 전류모드제어기를 설계하였다. 소신호 모델을 이용함으로써 부스투, 벅, 벅-부스트 컨버터에 모두 적용 가능한 데드빗 전류모드제어기를 설계 가능하고, 설계한 제어기는 모든 시비율 동작 조건에서 안정함을 확인하였다. 16bit 마이크로컨트롤러인 80C196KC를 사용하여 설계된 디지털 제어기를 구현하고, 아날로그제어기를 이용한 전류모드 제어에서의 동작 조건에 따른 불안정성 문제를 해결할 수 있음을 실험을 통해 확인하였다.