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http://dx.doi.org/10.5370/KIEE.2011.60.2.325

A 10bit 1MS/s 0.5mW SAR ADC with Double Sampling Technique  

Lee, Ho-Kyu (고려대학교 공과대학 전자전기공학과)
Kim, Moo-Young (고려대학교 공과대학 전자전기공학과)
Kim, Chul-Woo (고려대학교 공과대학 전자전기공학과)
Publication Information
The Transactions of The Korean Institute of Electrical Engineers / v.60, no.2, 2011 , pp. 325-329 More about this Journal
Abstract
This paper introduces the 10b 1MS/s SAR ADC with double sampling technique to reduce the power consumption. The SAR ADC is implemented in CMOS 1P8M 65nm technology and occupies 0.11um2. The maximum sampling rate is 1MS/s. The simulated SNDR and SFDR are 55.6dB and 62.7dB at 484kHz input frequency, respectively. The implemented data converter consumes 507uW with 1.2-V supply.
Keywords
SAR; ADC; Data converter; Double sampling; 1MS/s; 10b;
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