• Title/Summary/Keyword: 디지털 보정기법

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1V 1.6-GS/s 6-bit Flash ADC with Clock Calibration Circuit (클록 보정회로를 가진 1V 1.6-GS/s 6-bit Flash ADC)

  • Kim, Sang-Hun;Hong, Sang-Geun;Lee, Han-Yeol;Park, Won-Ki;Lee, Wang-Yong;Lee, Sung-Chul;Jang, Young-Chan
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.9
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    • pp.1847-1855
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    • 2012
  • A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are $800{\times}500{\mu}m2$ and 193.02mW.

Image Recovery Using Nonlinear Modeling of Industrial Radiography (산업용방사선영상의 비선형모델링에 의한 영상복구)

  • Hwang, Jung-Won;Hwang, Jae-Ho
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.45 no.4
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    • pp.71-77
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    • 2008
  • This paper presents a methodology for recovering the industrial radiographic images from the effects of nonlinear distortion. Analytical approach based on the inverse square law and Beer's law is developed in order to improve a mathematic model of nonlinear type. The geometric effect due to dimensions of the radioactive source appeals on the digitized images. The relation that expresses parameters values(angle, position, absorption coefficient, length, width and pixel account) is defined in this model, matching with the sample image. To perform the search for image recovery most similar to the model, a correction procedure is designed. The application of this method on the radiographic images of steel tubes is shown and recovered results are discussed.

Application of AI technology for various disaster analysis (다양한 재해분석을 위한 AI 기술적용 사례 소개)

  • Giha Lee;Xuan-Hien Le;Van-Giang Nguyen;Van-Linh Ngyen;Sungho Jung
    • Proceedings of the Korea Water Resources Association Conference
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    • 2023.05a
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    • pp.97-97
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    • 2023
  • 최근 재해분야에서 인공신경망(ANN), 기계학습(ML), 딥러닝(DL) 등 AI 기술이 활용성이 점차 증가하고 있으며, 센싱정보와 연계한 시설물 안전관리, 원격탐사와 연계한 재해감시(녹조, 산사태, 산불 등), 수문시계열(수위, 유량 등) 예측, 레이더·위성강수 자료의 보정과 예측, 상하수도 관망누수예측 등 다양한 분야에서 AI 기술이 적용되고 그 활용성이 검증된 바 있다. 본 연구에서는 ML, DL, 물리기반신경망(Pysics-informed Neural Networks, PINNs)을 이용한 다양한 재해분석 사례를 소개하고, 그 활용성과 한계에 대해서 논의하고자 한다. 주요사례로는 (1) SAR영상과 기계학습을 이용한 재해피해지역(울진 산불) 감지, (2) 국가 디지털 정보를 이용한 산사태 위험지역 판별(인제 산사태) (3) 기계학습 및 딥러닝 기법을 이용한 위성강수 자료의 보정·예측 및 유출해석, (4) 수리해석을 위한 수치해석분야에서의 PINNs의 적용성(1차원 Saint-Venant 식 해석) 평가 연구결과를 공유한다. 특히, 자료의 입·출력 자료만으로 학습된 인공신경망 모형 대신 지배방정식(물리방정식)을 만족하도록 강제한 PINNs의 경우, 인공신경망 모형보다 우수한 모의능력을 보여주었으며, 향후 복잡한 수리모델링 등 수치해석분야에서 그 활용가능성이 매우 높을 것으로 판단된다.

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FPGA Implementation of RVDT Digital Signal Conditioner with Phase Auto-Correction based on DSP (RVDT용 DSP 기반 위상 자동보정 디지털 신호처리기 FPGA 구현)

  • Kim, Sung-mi;Seo, Yeon-ho;Jin, Yu-rin;Lee, Min-woong;Cho, Seong-ik;Lee, Jong-yeol
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.21 no.6
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    • pp.1061-1068
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    • 2017
  • A RVDT is a sensor that measures angular displacement and the output signal of RVDT is a DSBSC-AM signal. For this reason, a DSBSC-AM demodulation processor is required to determine the angular displacement from the output signal. In this paper, DADC(Digital Angle to DC) which extracts the angular displacement from the output signal of a RVDT is implemented based-on modified Costas Loop usually used in the demodulation of DSBSC-AM signal by using FPGA. DADC can used with both 4-wire and 5-wire RVDTs and can exactly compensate the phase difference between the input excitation and output signals of a RVDT unlike the conventional analog RVDT signal conditioners which require external components. Since digital signal processing technique that can enhance the linearity is exploited, DADC shows 0.035% linearity error, which is smaller than 0.005% that of a conventional analog signal conditioner. The DADC are tested in an integrated experimental environment which includes a commercial RVDT sensor, ADC and an analog output block.

High-Resolution Sentinel-2 Imagery Correction Using BRDF Ensemble Model (BRDF 앙상블 모델을 이용한 고해상도 Sentinel-2 영상 보정)

  • Hyun-Dong Moon;Bo-Kyeong Kim;Kyeong-Min Kim;Subin Choi;Euni Jo;Hoyong Ahn;Jae-Hyun Ryu;Sung-Won Choi;Jaeil Cho
    • Korean Journal of Remote Sensing
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    • v.39 no.6_1
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    • pp.1427-1435
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    • 2023
  • Vegetation indices based on selected wavelength reflectance measurements are used to represent crop growth and physiological conditions. However, the anisotropic properties of the crop canopy surface can govern spectral reflectance and vegetation indices. In this study, we applied an ensemble of bidirectional reflectance distribution function (BRDF) models to high-resolution Sentinel-2 satellite imagery and compared the differences between correction results before and after reflectance. In the red and near-infrared (NIR) band reflectance images, BRDF-corrected outlier values appeared in certain urban and paddy fields of farmland areas and forest shadow areas. These effects were equally observed when calculating the normalized difference vegetation index (NDVI) and 2-band enhanced vegetation index (EVI2). Furthermore, the outlier values in corrected NIR band were shown in pixels shadowed by mountain terrain. These results are expected to contribute to the development and improvement of BRDF models in high-resolution satellite images.

A 2.5 Gb/s Burst-Mode Clock and Data Recovery with Digital Frequency Calibration and Jitter Rejection Scheme (디지털 주파수 보정과 지터 제거 기법을 적용한 2.5 Gb/s 버스트 모드 클럭 데이터 복원기)

  • Jung, Jae-Hun;Jung, Yun-Hwan;Shin, Dong Ho;Kim, Yong Sin;Baek, Kwang-Hyun
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.7
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    • pp.87-95
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    • 2013
  • In this paper, 2.5 Gb/s burst-mode clock and data recovery(CDR) is presented. Digital frequency calibration scheme is adopted to eliminate mismatch between the input data rate and the output frequency of the gated voltage controlled oscillator(GVCO) in the clock recovery circuitry. A jitter rejection scheme is also used to reduce jitter caused by input data. The proposed burst-mode CDR is designed using 0.11 ${\mu}m$ CMOS technology. Post-layout simulations show that peak-to-peak jitter of the recovered data is 14 ps with 0.1 UI input referred jitter, and maximum tolerance of consecutive identical digit(CID) is 2976 bits without input data jitter. The active area occupies 0.125 $mm^2$ without loop filter and the total power consumption is 94.5 mW.

On-Chip Full CMOS Current and Voltage References for High-Speed Mixed-Mode Circuits (고속 혼성모드 집적회로를 위한 온-칩 CMOS 전류 및 전압 레퍼런스 회로)

  • Cho, Young-Jae;Bae, Hyun-Hee;Jee, Yong;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.40 no.3
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    • pp.135-144
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    • 2003
  • This work proposes on-chip full CMOS current and voltage references for high-speed mixed-mode circuits. The proposed current reference circuit uses a digital-domain calibration method instead of a conventional analog calibration to obtain accurate current values. The proposed voltage reference employs internal reference voltage drivers to minimize the high-frequency noise from the output stages of high-speed mixed-mode circuits. The reference voltage drivers adopt low power op amps and small- sized on-chip capacitors for low power consumption and small chip area. The proposed references are designed, laid out, and fabricated in a 0.18 um n-well CMOS process and the active chip area is 250 um x 200 um. The measured results show the reference circuits have the power supply variation of 2.59 %/V and the temperature coefficient of 48 ppm/$^{\circ}C$ E.

JND based Illumination and Color Restoration Using Edge-preserving Filter (JND와 경계 보호 평탄화 필터를 이용한 휘도 및 색상 복원)

  • Han, Hee-Chul;Sohn, Kwan-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.46 no.6
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    • pp.132-145
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    • 2009
  • We present the framework for JND based Illumination and Color Restoration Using Edge-preserving filter for restoring distorted images taken under the arbitrary lighting conditions. The proposed method is effective for appropriate illumination compensation, vivid color restoration, artifacts suppression, automatic parameter estimation, and low computation cost for HW implementation. We show the efficiency of the mean shift filter and sigma filter for illumination compensation with small spread parameter while considering the processing time and removing the artifacts such as HALO and noise amplification. The suggested CRF (color restoration filter) can restore the natural color and correct color distortion artifact more perceptually compared with current solutions. For the automatic processing, the image statistics analysis finds suitable parameter using JND and all constants are pre-defined. We also introduce the ROI-based parameter estimation dealing with small shadow area against spacious well-exposed background in an image for the touch-screen camera. The object evaluation is performed by CMC, CIEde2000, PSNR, SSIM, and 3D CIELAB gamut with state-of-the-art research and existing commercial solutions.

Fabrication of High Frequency Magnetic Characteristics Measurement System Using Digital Oscilloscope and Computer Remote Control (디지털 오실로스코프와 컴퓨터 제어기법을 이용한 고주파 자기특성 측정장치 제작)

  • 김기옥;이재복;송재성;민복기
    • Journal of the Korean Magnetics Society
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    • v.7 no.6
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    • pp.327-333
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    • 1997
  • We designed and constructed the high frequency magnetic characteristics measurement system to measure core loss, B-H curve, permeability of toroidal ferrite core, amorphous core and various materials for high frequency application. The system consists of universal equipments such as digitizing oscilloscope, signal generator, power amplifier, PC in order to make upgrade easily. The power source is composed of waveform synthesizer and power amplifier ranging from DC to 20 MHz, and output signal H and B from sample core are digitized by oscilloscope with sampling rate 1 GS/ s per channel. Computer controls power source and oscilloscope, reads data from oscilloscope, displays analyzed waveform and saves data with file. The entire procedures finishes within few seconds.

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Image Tracking Based Lane Departure Warning and Forward Collision Warning Methods for Commercial Automotive Vehicle (이미지 트래킹 기반 상용차용 차선 이탈 및 전방 추돌 경고 방법)

  • Kim, Kwang Soo;Lee, Ju Hyoung;Kim, Su Kwol;Bae, Myung Won;Lee, Deok Jin
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.39 no.2
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    • pp.235-240
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    • 2015
  • Active Safety system is requested on the market of the medium and heavy duty commercial vehicle over 4.5ton beside the market of passenger car with advancement of the digital equipment proportionally. Unlike the passenger car, the mounting position of camera in case of the medium and heavy duty commercial vehicle is relatively high, it is disadvantaged conditions for lane recognition in contradiction to passenger car. In this work, we show the method of lane recognition through the Sobel edge, based on the spatial domain processing, Hough transform and color conversion correction. Also we suggest the low error method of front vehicles recognition in order to reduce the detection error through Haar-like, Adaboost, SVM and Template matching, etc., which are the object recognition methods by frontal camera vision. It is verified that the reliability over 98% on lane recognition is obtained through the vehicle test.