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http://dx.doi.org/10.6109/jkiice.2017.21.6.1061

FPGA Implementation of RVDT Digital Signal Conditioner with Phase Auto-Correction based on DSP  

Kim, Sung-mi (Department of Electronic Engineering, Chonbuk National University)
Seo, Yeon-ho (Department of Electronic Engineering, Chonbuk National University)
Jin, Yu-rin (Department of Electronic Engineering, Chonbuk National University)
Lee, Min-woong (Department of Electronic Engineering, Chonbuk National University)
Cho, Seong-ik (Department of Electronic Engineering, Chonbuk National University)
Lee, Jong-yeol (Department of Electronic Engineering, Chonbuk National University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.21, no.6, 2017 , pp. 1061-1068 More about this Journal
Abstract
A RVDT is a sensor that measures angular displacement and the output signal of RVDT is a DSBSC-AM signal. For this reason, a DSBSC-AM demodulation processor is required to determine the angular displacement from the output signal. In this paper, DADC(Digital Angle to DC) which extracts the angular displacement from the output signal of a RVDT is implemented based-on modified Costas Loop usually used in the demodulation of DSBSC-AM signal by using FPGA. DADC can used with both 4-wire and 5-wire RVDTs and can exactly compensate the phase difference between the input excitation and output signals of a RVDT unlike the conventional analog RVDT signal conditioners which require external components. Since digital signal processing technique that can enhance the linearity is exploited, DADC shows 0.035% linearity error, which is smaller than 0.005% that of a conventional analog signal conditioner. The DADC are tested in an integrated experimental environment which includes a commercial RVDT sensor, ADC and an analog output block.
Keywords
RVD; Signal Conditioner; Digital; Phase Auto-Correction; Costas Loop;
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