• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.3
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• pp.18-24
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• 2011

This paper presents that the yield strength of the pressure sensor with a double boss diaphragm structure can be improved as the grooves are formed at the corner of the diaphragm bridge. Generally the boss structure is widely used for the low-pressure sensor, of which the sensitivity is not enough in case of the small diaphragm size limited by a chip size constraint. The double boss structure pressure sensor exhibits a great sensitivity, but suffers from the low yield strength problem due to the high stress occurred at the corner of the diaphragm bridge to be limited in the operating range. ANSYS simulation is performed by changing the length of the groove from 0.5${\mu}m$ to 10${\mu}m$ at the corner of the diaphragm bridge of the double boss structure pressure sensor. The maximum stress is analyzed at the corner of the diaphragm bridge, the edge of the diaphragm bridge, and the position of the piezoresistive sensor. Consequently, in case the length of the groove from the edge of the diaphragm is 6${\mu}m$ or greater, the stress occurred in the corner of the bridge is less than the stress acting on a piezoresistive element.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.34-42
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• 2014

This paper presents a low-complexity and high-throughput symbol detector for two-spatial-stream multiple-input multiple-output systems based on the modified maximum-likelihood symbol detection algorithm. In the proposed symbol detector, the cost function is calculated incrementally employing a multi-cycle architecture so as to eliminate the complex multiplications for each symbol, and the slicing operations are performed hierarchically according to the range of constellation points by a pipelined architecture. The proposed architecture exhibits low hardware complexity while supporting complicated modulations such as 256 QAM. In addition, various modulations and antenna configurations are supported flexibly by reconfiguring the pipeline for the slicing operation. The proposed symbol detector is implemented with 38.7K logic gates in a $0.11-{\mu}m$ CMOS process and its throughput is 166 Mbps for $2{\times}$3 16-QAM and 80Mbps for $2{\times}3$ 64-QAM where the operating frequency is 478 MHz.

• Journal of IKEEE
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• v.2 no.1 s.2
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• pp.34-41
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• 1998

An integrated circuit for magnetic stripe storage system is implemented. All the analog and digital circuits are integrated in one chip. The analog block contains preamplifier, peak detecter, comparator and reference generater. And digital block includes reference window signal generater, up/down counter for F/2F signal measurement, bit-error detection logic, and control logic. Both the encoding and decoding functions for F/2F signal processing are provided. An AGC(automatic gain control) circuit which was included in conventional circuits is eliminated due to optimized circuit design. Misreading prevention circuits are also proposed by fixing up new reference bit when broken bits are detected. The prototype chip is implemented using $0.8{\mu}m$ N-well CMOS technology and operates from 3.3 V to 7.5 V of supply voltage. It occupies a die area of $3.04mm^2(1.6mm{\times}1.9mm)$ and dissipates 8 mW with a 5 V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.9-17
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• 2000

A sensor array with 10 discrete sensors integrated on a substrate was developed for discriminating the kinds and quantities of explosive gases. The sensor array consisted of 10 oxide semiconductor gas sensors with $SnO_2$ as base material and had broad sensitivity to specific gas. The sensor array was designed with uniform thermal distribution and had also high sensitivity and reproductivity to low gas concentration through nano-sized sensing materials with different additives. By using the sensitivity signal of the sensor array at $400^{\circ}C$, we could reliably discriminate the kinds and quantities of explosive gases like butane, propane and methane under the lower explosion limit through the principal component analysis (PCA) method.

• The Journal of the Korea Contents Association
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• v.14 no.10
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• pp.210-217
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• 2014

This study is to present objective data for the approaches of therapeutic exercise for the correction of genu varum by making an analysis and a comparison of the hip joints' ROM and isokinetic muscles of the female college students with straight legs with those of a female college student with idiopathic genu varum. Additionally, the state of the adductor muscle's thighs and the deep muscles of the subjects with bowed legs were experimented and the equipment's effect and applicability was reviewed through the process of the movement of newly developed exercise equipment, Balloa(2013, Balloa/Adonia/Korea). As a result, a person with genu varum needs the height increasing method for increasing external rotation ROM of a hip joint and requires the exercise techniques to strengthen external rotator muscles and to inhibit the activity of internal rotator muscles of a hip joint. Balloa increases the external rotation ROM of a hip joint and strengthens gluteal muscles, deep muscles, and adductor muscles, and the equipment's function of muscle strengthening shows that the equipment is an effective corrective exercise for the patients of genu varum.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.39 no.2
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• pp.137-142
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• 2015

Teleoperation of a robot arm working in hazardous environments has been studied in the field of defense and security. A master system is an essential part that plays an important role in the teleoperation. We developed a master system, which is an essential part in the teleoperation, so that it can operate the slave robot arm intuitively and has excellent mobility and portability compared to conventional master systems. The master system adopted a Stewart platform to minimize the size and weight, and the legs of the Stewart platform are composed of wires to improve the operation range of the system. The experimental validation of the developed master system is conducted with a commercial IMU, and the experimental results show that the proposed master system can perform reliable and dexterous teleoperation.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.63-70
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• 2013

This paper describes a high PSRR low-dropout(LDO) linear regulator for wide frequency range without output-capacitor. Owing to both of the cascode compensation technique and the current buffer compensation technique in nested Miller compensation loop, the proposed LDO not only maintaines high stability but also achieves high PSRR over wide frequency range with reasonable on-chip capacitances. Since the external capacitor is removed by the proposed compensation techniques, the cost for pad is eliminated. The designed LDO works under the input voltage range from 2.5V to 4.5V and provides up to 10mA load current with the output voltage of 1.8V. The LDO was implemented with 0.18um CMOS technology and the area is 300um X 120 um. The measured power supply rejection ratio(PSRR) is -76dB and -43dB at DC and 1MHz, respectively. The operating current is 25uA.

• Journal of IKEEE
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• v.6 no.1 s.10
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• pp.21-29
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• 2002

This paper describes a high resolution DLL(Delay Locked Loop) using all digital circuits. The proposed architecture is based on the three stage of coarse, fine and ultra fine phase tuning block which has a phase detector, selection block and delay line respectively. The first stage, the ultra fine phase tuning block, is tune to accomplish high resolution using a vernier delay line. The second and third stage, the coarse and fine tuning block, are tuning the phase margin of Unit Delay using the delay line and are similar to each other. It was simulated in 0.35um CMOS technology under 3.3V supply using HSPICE simulator. The simulation result shows the phase resolution can be down to lops with the operating range of 250MHz to 800MHz.

• Journal of IKEEE
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• v.3 no.2 s.5
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• pp.186-195
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• 1999

In this paper, the RF-modules composed of front-end, frequency synthesizer, modulator/demodulator and power control multi channel WLL personal system for W-CDMA using 10 [MHz] RF channel bandwidth has been implemented and considered. The measured transmission power is 250 [mW] which is very close to the required value. The measured flatness of power at the final output stage is ${\pm}1.5[dB]$ over the required bandwidth of the receiver. In addition, it is found that the chip rate transmitting spread signal is set to 8.192 [MHz], the required rate. The frequencies of RF_LO signal and LO signal of the modulator and the demodulator measured by a frequency synthesizer are satisfied with design requirements. The operating range of the receiving strength signal indicator and AGC units shows 60 [dB] respectively. Also the measured phasor diagram and eye pattern for deciding the RF modules compatible with baseband digital signal processing part are shown good results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.36-42
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• 2009

This paper proposes the high-performance pipeline architecture for modified Booth multipliers. The proposed multiplier circuits are based on modified Booth algorithm and pipeline architecture which are the most widely used techniques to accelerate the multiplication speed. In order to implement the optimally pipelined multipliers, many kinds of experiments have been conducted. The experimental results show that the speed improvement gain exceeds the area penalty and this trend is manifested as the number of pipeline stages increases. It is also important to insert the pipeline registers at the proper positions. We described the proposed modified Booth multiplier circuits in Verilog HDL and synthesized the gate-level circuits using 0.13um standard cell library. The resultant multiplier circuits show better performance than others. Since they operate at GHz ranges, they can be used in the application systems requiring extremely high performance such as optical communication systems.