• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.39A no.5
• /
• pp.251-257
• /
• 2014

Digital RDA system is retransmit into the opposite direction of the incident signals. Digital RDA system have a disadventage that this system do not signal classification in multipath environment. because multipath signal is shown as vector sum of multipath signal, digital RDA system required complex signal process for multipath signal classification. In this paper, to solve these problem we propose hybrid digital RDA system which combination of the MUSIC algorithm and the digital RDA system. Proposed system has two modes. First mode is digital RDA mode. Secornd mode is digital beamforming mode. Digital RDA mode is used in situations where the less the impact of multipath. Digital beamforming mode is applied to multipath effects is greater. In secornd mode, we find optimal path using MUSIC algorithm. After than the proposed system uses only the optimal path. Through the proposed system in a multipath environment with digital RDA can be used to supplement a disadvantage.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.6 no.5
• /
• pp.423-431
• /
• 2001

This paper proposes a new active common-mode voltage damper circuit that is capable of suppressing a common-mode voltage produced in the PWM VSI-fed induction motor drives. The new active common mode voltage damper is consists of a four-level half-bridge Inverter and a common mode transformer with a blocking capacitor. In order to reduce the common mode voltage and high frequency leakage current the active common mode damper applies to the PWM inverter system the compensated voltage of which the amplitude is the same as the common mode voltage and of which the polarity is opposite to the common mode voltage. Simulated using P-SPICE and experimental results show that common-mode voltage damper makes contributions to reducing a high frequency leakage current and common-mode voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.11
• /
• pp.9-16
• /
• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.54 no.6
• /
• pp.30-39
• /
• 2017

A digital calibration technique based on digital-domain averaging for cyclic ADC is proposed. The proposed calibration compensates for nonlinearity of ADC due to capacitance mismatch of capacitors in 1.5-bit/stage MDAC. A 1.5-bit/stage MDAC with non-matched capacitors has symmetric residue plots with respect to the ideal residue plot. This intrinsic characteristic of residue plot of MDAC is reflected as symmetric A/D transfer functions. A corrected A/D transfer function can be acquired by averaging two transfer functions with non-linearity, which are symmetric with respect to the ideal analog-digital transfer function. In order to implement the aforementioned averaging operation of analog-digital transfer functions, a 12-bit cyclic ADC of this work defines two operational modes of 1.5-bit/stage MDAC. By operating MDAC as the first operational mode, the cyclic ADC acquires 12.5-bits output code with nonlinearity. For the same sampled input analog voltage, the cyclic ADC acquires another 12.5-bits output code with nonlinearity by operating MDAC as the second operational mode. Since analog-digital transfer functions from each of operational mode of 1.5-bits/stage MDAC are symmetric with respect to the ideal analog-digital transfer function, a corrected 12-bits output code can be acquired by averaging two non-ideal 12.5-bits codes. The proposed digital calibration and 12-bit cyclic ADC are implemented by using a $0.18-{\mu}m$ CMOS process in the form of full custom. The measured SNDR(ENOB) and SFDR are 65.3dB (10.6bits) and 71.7dB, respectively. INL and DNL are measured to be -0.30/-0.33LSB and -0.63/+0.56LSB, respectively.

• Proceedings of the KIPE Conference
• /
• 2020.08a
• /
• pp.73-75
• /
• 2020

• Journal of IKEEE
• /
• v.25 no.1
• /
• pp.218-228
• /
• 2021

This paper presents the high-efficiency DC-DC converter using the multi-resonant-circuit. The proposed converter has the power topology of half-bridge and utilizes the multi-resonant-circuit that is composed of 2 inductors (LL) and 1 capacitor (C) to achieve high-efficiency. The multi-resonant-circuit forms each resonant circuit of series circuit type with each resonant frequency, according to the operation modes. This paper first describes the operation pirinciples of proposed converter by the operation modes and steady-state fundamental approximation modelling. Then it shows a design example of the proposed converter based on the principles. And it is validated that the proposed converter has the operation characteristics of high-efficiency DC-DC power conversion through the experimental results of prototype converter implemented by the designed circuit parameters.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.13 no.9
• /
• pp.1837-1844
• /
• 2009

In this paper, the circuit of 2 variable ternary adder and multiplier circuit using current mode CMOS are implemented. The presented ternary adder circuit and multiplier circuit using current mode CMOS are driven the voltage levels. We show the characteristics of operation for these circuits simulated by HSpice. These circuits are simulated under $0.18{\mu}m$ CMOS standard technology, $5{\mu}A$ unit current in $0.54{\mu}m/0.18{\mu}m$ ratio of NMOS length and width, and $0.54{\mu}m/0.18{\mu}m$ ratio of PMOS length and width, and 2.5V VDD voltage, MOS model Level 47 using HSpice. The simulation results show the satisfying current characteristics. The simulation results of current mode ternary adder circuit and multiplier circuit show the propagation delay time $1.2{\mu}s$, operating speed 300KHz, and consumer power 1.08mW.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.22 no.2
• /
• pp.162-168
• /
• 2008

In this paper, the RCF(Resistive Companion Form) analysis method is applied to analyze small signal stability of power systems including thyristor controlled FACTS(Flexible AC Transmission System) equipments such as TCSC(Thyristor Controlled Series Capacitor). The eigenvalue sensitivity analysis algorithm in discrete systems based on the RCF analysis method is presented and applied to the power system including TCSC. As a result of simulation, the RCF analysis method is very useful to precisely calculate the variations of eigenvalues or newly generated unstable oscillation modes after periodic switching operations of TCSC. Also the eigenvalue sensitivity analysis method based on the RCF analysis method enabled to precisely calculate eigenvalue sensitivity coefficients of controller parameters about the dominant oscillation mode after periodic switching operations in discrete systems. These simulation results are different from those of the conventional continuous system analysis method such as the state space equation and showed that the RCF analysis method is very useful to analyze the discrete power systems including periodically operated switching equipments such as TCSC.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.12 no.5
• /
• pp.15-25
• /
• 2002

In this paper a design of high performance cryptographic processor which implements AES Rijndael algorithm is described. To eliminate performance degradation due to round-key computation delay of conventional processor, the on-the-fly precomputation of round key based on modified round structure is adopted. And on-the-fly round key generator which supports 128, 192, and 256-bit key has modular structure. The designed processor has iterative structure which uses 1 clock cycle per round and supports three operation modes, such as ECB, CBC, and CTR mode which is a candidate for new AES modes of operation. The cryptographic processor designed in Verilog-HDL and synthesized using 0.251$\mu\textrm{m}$ CMOS cell library consists of about 51,000 gates. Simulation results show that the critical path delay is about 7.5ns and it can operate up to 125Mhz clock frequency at 2.5V supply. Its peak performance is about 1.45Gbps encryption or decryption rate under 128-bit key ECB mode.

• Proceedings of the KIEE Conference
• /
• 2011.07a
• /
• pp.1158-1160
• /
• 2011

본 논문에서는 에너지저장 커패시터 충전용 직렬공진형 컨버터의 운용모드별 충전특성을 비교하였다. 커패시터 부하를 갖는 풀브릿지 직렬공진형 컨버터의 운용모드별 동작원리를 설명하고 해석하였다. 운용모드별 충전특성을 충전시간, 스위치손실, 스위치이용률 측면에서 시뮬레이션을 통해 비교, 분석하였다. 1.8 kJ/s 컨버터를 설계하고, 실험을 통해 충전시간 특성에 대한 비교 결과를 제시하였다.