Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Digital Calibration Technique for Cyclic ADC based on Digital-Domain Averaging of A/D Transfer Functions

아날로그-디지털 전달함수 평균화기법 기반의 Cyclic ADC의 디지털 보정 기법

  • Um, Ji-Yong (Dept. of Electronic Engineering, Hannam University)
  • 엄지용 (한남대학교 전자공학과)
  • Received : 2017.01.04
  • Accepted : 2017.05.25
  • Published : 2017.06.25
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Abstract

A digital calibration technique based on digital-domain averaging for cyclic ADC is proposed. The proposed calibration compensates for nonlinearity of ADC due to capacitance mismatch of capacitors in 1.5-bit/stage MDAC. A 1.5-bit/stage MDAC with non-matched capacitors has symmetric residue plots with respect to the ideal residue plot. This intrinsic characteristic of residue plot of MDAC is reflected as symmetric A/D transfer functions. A corrected A/D transfer function can be acquired by averaging two transfer functions with non-linearity, which are symmetric with respect to the ideal analog-digital transfer function. In order to implement the aforementioned averaging operation of analog-digital transfer functions, a 12-bit cyclic ADC of this work defines two operational modes of 1.5-bit/stage MDAC. By operating MDAC as the first operational mode, the cyclic ADC acquires 12.5-bits output code with nonlinearity. For the same sampled input analog voltage, the cyclic ADC acquires another 12.5-bits output code with nonlinearity by operating MDAC as the second operational mode. Since analog-digital transfer functions from each of operational mode of 1.5-bits/stage MDAC are symmetric with respect to the ideal analog-digital transfer function, a corrected 12-bits output code can be acquired by averaging two non-ideal 12.5-bits codes. The proposed digital calibration and 12-bit cyclic ADC are implemented by using a $0.18-{\mu}m$ CMOS process in the form of full custom. The measured SNDR(ENOB) and SFDR are 65.3dB (10.6bits) and 71.7dB, respectively. INL and DNL are measured to be -0.30/-0.33LSB and -0.63/+0.56LSB, respectively.

본 논문은 디지털영역에서의 평균화 기법을 이용한 cyclic ADC의 디지털 보정기법을 제안한다. 제안하는 보정기법은 1.5비트 MDAC의 커패시터 부정합으로 인해 발생하는 ADC의 비선형성을 보정한다. 부정합을 지니는 커패시터로 이루어진 1.5비트 MDAC은 이상적인 1.5비트 MDAC의 레지듀 플롯(residue plot)에 대해 대칭적인 레지듀 플롯을 지닌다. 커패시터 부정합을 지니는 1.5비트 MDAC의 고유한 레지듀 플롯은 대칭적인 아날로그-디지털 전달함수로 반영된다. 이상적인 아날로그-디지털 전달함수에 대해 대칭적인 두 아날로그-디지털 전달함수를 평균화함으로써, 비선형성이 보정된 아날로그-디지털 전달함수를 얻을 수 있다. 해당 아날로그-디지털 전달함수 평균화의 구현을 위해, 본 논문의 12비트 cyclic ADC는 1.5비트 MDAC의 동작 모드를 2개로 정의한다. 해당 cyclic ADC는 MDAC을 첫 번째 동작모드로 동작시킴으로써, 비선형성을 지니는 12.5비트 출력 코드를 획득한다. 샘플링 된 동일한 입력 아날로그 전압에 대해, MDAC을 두 번째 동작모드로 동작시킴으로써, cyclic ADC는 비선형성을 지니는 또 다른 12.5비트 출력 코드를 획득한다. 각 MDAC의 동작모드에 의해 발생하는 아날로그-디지털 전달함수는 이상적인 아날로그-디지털 전달함수에 대해 대칭적이기 때문에, 앞서 획득한 두 개의 비선형성을 지니는 12.5비트를 평균화함으로써, 비선형성이 보정된 최종 12비트 출력 코드를 획득할 수 있다. 제안하는 디지털 보정기법과 12비트 cyclic ADC는 $0.18-{\mu}m$ CMOS 공정을 이용하여 full-custom 형식으로 구현되었다. 측정된 SNDR(ENOB)와 SFDR은 각각 65.3dB(10.6비트 ENOB)와 71.7dB이다. 측정된 INL과 DNL은 각각 -0.30/+0.33LSB와 -0.63/+0.56LSB이다.

Keywords

References

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