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http://dx.doi.org/10.13089/JKIISC.2002.12.5.15

Design of AES Cryptographic Processor with Modular Round Key Generator  

최병윤 (동의대학교 컴퓨터공학과)
박영수 (한국 전자 통신 연구원 정보 보호 기술 연구 본부)
전성익 (한국 전자 통신 연구원 정보 보호 기술 연구 본부)
Abstract
In this paper a design of high performance cryptographic processor which implements AES Rijndael algorithm is described. To eliminate performance degradation due to round-key computation delay of conventional processor, the on-the-fly precomputation of round key based on modified round structure is adopted. And on-the-fly round key generator which supports 128, 192, and 256-bit key has modular structure. The designed processor has iterative structure which uses 1 clock cycle per round and supports three operation modes, such as ECB, CBC, and CTR mode which is a candidate for new AES modes of operation. The cryptographic processor designed in Verilog-HDL and synthesized using 0.251$\mu\textrm{m}$ CMOS cell library consists of about 51,000 gates. Simulation results show that the critical path delay is about 7.5ns and it can operate up to 125Mhz clock frequency at 2.5V supply. Its peak performance is about 1.45Gbps encryption or decryption rate under 128-bit key ECB mode.
Keywords
AES(Advanced Encryption Standard); Key Scheduler; Block Cipher; Cryptographic Processor;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
연도 인용수 순위
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