• Journal of KIISE:Computer Systems and Theory
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• v.34 no.2
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• pp.84-92
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• 2007

This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller and simplifies the test procedure and reduces the area overhead.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.3C
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• pp.302-313
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• 2010

In this paper, we propose an enhanced AGC (Automatic Gain Control) structure and P-SCH detection method for initial cell search in 3GPP (3rdGenerationPartnershipProject) LTE (Long Term Evolution) FDD(Frequency Division Duplex) / TDD (Time Division Duplex) dual mode system. Since TDD frame structure consists of uplink subframe and downlink subframe, conventional AGC structure causes P-SCH detection performance degradation by increase of AGC variation due to signal power difference between uplink and downlink subframe. Also, P-SCH detection performance is degraded by distortion of P-SCH correlation characteristic in frequency offset and multipath fading channel environments. Therefore, we propose an AGC structure which can minimize P-SCH detection performance degradation with stable operation in 3GPP LTE TDD mode as well as FDD mode. Also we propose a P-SCH detection method which can reduce distortion of correlation chareteristics in frequency offset and multipath fading environments and obtain good P-SCH detection performance. Simulation results show that the proposed AGC structure and P-SCH detection method have stable AGC operation and excellent P-SCH detection performance for 3GPP LTE TDD / FDD dual mode downlink receiver in various channel environments.

• Korean Journal of Optics and Photonics
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• v.4 no.2
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• pp.212-219
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• 1993

To reduce the mode noise induced from a multimode dye laser, a modeless laser generating amplified spontaneous emission was used as Stokes beam of the broadband CARS. A new technique for measuring species concentration from the modulation dip of nonresonant background of broadband CARS spectrum was proposed. The modulation dip was numerically calculated and fitted as a function of the concentration of the minor species and temperature of gas sample. We applied this technique in measuring CO concentration in a static cell and also the profile of CO concentration in a CHdair premixed flame of a counterflow burner.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2465-2473
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• 2011

This paper describes a circuit-level optimization of DFU(decoding function unit) for LDPC decoder which is used in wireless communication systems including WiMAX and WLAN. A new design of DFU based on sign-magnitude arithmetic instead of two's complement arithmetic is proposed, resulting in 18% reduction of gate count for 96 DFUs array used in mobile WiMAX LDPC decoder. A multi-mode LDPC decoder for mobile WiMAX standard is designed using the proposed DFU. The LDPC decoder synthesized using a 0.18-${\mu}m$ CMOS cell library with 50 MHz clock has 268,870 gates and 71,424 bits RAM, and it is verified by FPGA implementation.

• Information and Communications Magazine
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• v.32 no.2
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• pp.114-116
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• 2015

점점 더 가속화하고 있는 이동통신 기술의 진보에서 비롯된 통신 환경의 변화는 폭증하는 데이터 트래픽에 대한 효율적인 관리 제어를 요구하고 있으며, 이러한 요구에 대응한 다양한 방식의 시스템들이 개발되고 있다. 이 중에서 RU(Radio Unit)와 DU(Digital Unit)의 분리 및 관련 기술의 고도화는 이동통신 시스템 환경 구축의 효율성과 유연성을 제고하는 신기술 방식으로 자리 잡고 있다. 본 고에서는 RF 처리부를 소형 모듈화한 RF 단위모듈을 이용하여 RU를 구현함으로써, 다양한 용량과 서비스 영역을 제공할 수 있는 기지국 솔루션 개발현황을 소개하고자 한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.37-44
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• 2006

This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller is simple in terms of test procedure and is small in terms of area overhead.

• Information and Communications Magazine
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• v.31 no.3
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• pp.85-95
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• 2014

통신 사업자들은 과거에 통신 사업자 주도의 Walled Garden 형태의 제한적인 컨텐츠 서비스 제공 및 음성 중심의 시대에서 트래픽의 증가에 비례하는 수익의 증가를 경험하였다. 그러나 스마트폰의 보급과 함께 사용자들이 필요한 컨텐츠에 직접 접속하는 개방형 서비스의 수용 및 데이터 중심의 시대로 전환되면서 통신 사업자의 수익은 처리 트래픽의 증가에 비례 하지 않고 정체되어 있고 모바일 데이터 폭증에 따른 망 인프라 투자 및 유지보수 비용을 계속 늘려야 하는 상황에 직면하게 되었다. 본 고에서는 통신 사업자들의 이러한 국면을 타개하기 위한 제도적, 사업적 그리고 기술적인 해결책 중에서 기술적인 측면의 한 분야로 평가되고 있는 클라우드 기지국 전반에 대하여 살펴본다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.164-166
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• 2016

PRESENT/ARIA/AES의 3가지 블록 암호 알고리즘을 지원하는 암호 프로세서를 MPW(Multi-Project Wafer)칩으로 구현하였다. 설계된 블록 암호 칩은 PRmo(PRESENT with mode of operation) 코어, AR_AS(ARIA_AES) 코어, AES-16b 코어로 구성된다. PRmo는 80/128-비트 마스터키와, ECB, CBC, OFB, CTR의 4가지 운영모드를 지원한다. 128/256-비트 마스터키를 사용하는 AR_AS 코어는 서로 내부 구조가 유사한 ARIA와 AES를 통합하여 설계하였다. AES-16b는 128-비트 마스터키를 지원하고, 16-비트 datapath를 채택하여 저면적으로 구현하였다. 설계된 암호 프로세서를 FPGA검증을 통하여 정상 동작함을 확인하였고, 0.18um 표준 셀 라이브러리로 논리 합성한 결과, 100 KHz에서 52,000 GE로 구현이 되었으며, 최대 92 MHz에서 동작이 가능하다. 합성된 다중 암호 프로세서는 MPW 칩으로 제작될 예정이다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.18-26
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n wireless LAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. From fixed-point modeling and Matlab simulations for various bit-widths, decoding performance and optimal hardware parameters such as fixed-point bit-width are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.18-${\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.2A
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• pp.128-137
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• 2006

In this paper, we propose a wireless network discovery scheme which support effective device power management by employing battery efficient network scanning procedure. Multi-mode terminals need to discover other wireless systems, above all, to execute an inter-system handover in the environment of heterogeneous wireless networks. The existing methods introduced in some recent research reports have certain shortcomings, such as battery power consumption increased by frequent modem activation, or the multi-mode terminal's inability to promptly discover wireless system. We Propose a scheme in which multi-mode terminals more quickly and accurately discover other wireless systems than previous schemes, while consuming minimum power. It also proves that the scheme has better performance by comparing it with the existing schemes.