• Proceeding of EDISON Challenge
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• 2016.03a
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• pp.365-367
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• 2016

나노와이어 FET은 natural length가 작아 단채널 효과가 MOSFET에 비해 줄어든다는 장점이 있어 미래의 소자 구조로 주목 받고 있다. 그런데 나노와이어 FET을 공정할 때 채널 etching에서 채널이 완벽하게 원형 구조를 가지는 것이 어렵다. 본 논문에서는 gate-all-around 실리콘 나노와이어 FET의 aspect ratio에 따른 트랜지스터의 특성 변화를 알아 보았다. 시뮬레이션 결과, aspect ratio가 작을수록 나노와이어 FET에서의 단채널 효과가 줄어드는 경향을 보였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.9
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• pp.1771-1777
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• 2016

In this thesis, the breakdown voltage characteristics of silicon nanowire N-channel GAA MOSFETs were analyzed through experiments and 3-dimensional device simulation. GAA MOSFETs with the gate length of 250nm, the gate dielectrics thickness of 6nm and the channel width ranged from 400nm to 3.2um were used. The breakdown voltage was decreased with increasing gate voltage but it was increased at high gate voltage. The decrease of breakdown voltage with increasing channel width is believed due to the increased current gain of parasitic transistor, which was resulted from the increased potential in channel center through floating body effects. When the positive charge was trapped into the gate dielectrics after gate stress, the breakdown voltage was decreased due to the increased potential in channel center. When the negative charge was trapped into the gate dielectrics after gate stress, the breakdown voltage was increased due to the decreased potential in channel center. We confirmed that the measurement results were agreed with the device simulation results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.9
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• pp.24-29
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• 2010

This paper presents the RF modeling for silicon nanowire MOSFET with 30 nm channel length and 5 nm channel radius. Equations for analytical parameter extraction are derived by analysis of Y-parameter. Accuracies of the new model and extracted parameters have been verified by 3-dimensional device simulation data up to 100 GHz. The model verifications are performed under conditions of saturation region ($V_{gs}$ = $_{ds}$ = 1 V) and linear region ($V_{gs}$ = 1 V, $V_{ds}$ = 0.5 V). The RMS modeling error of Y-parameters was calculated to be 1 %.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.793-798
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• 2016

In this work, the memory window characteristics of vertical nanowire device with asymmetric source and drain was analyzed using bipolar junction transistor mode for 1T-DRAM application. A gate-all-around (GAA) MOSFET with higher doping concentration in the drain region than in the source region was used. The shape of GAA MOSFET was a tapered vertical structure that the source area is larger than the drain area. From hysteresis curves using bipolar junction mode, the memory windows were 1.08V in the forward mode and 0.16V in the reverse mode, respectively. We observed that the latch-up point was larger in the forward mode than in the reverse mode by 0.34V. To confirm the measurement results, the device simulation has been performed and the simulation results were consistent in the measurement ones. We knew that the device structure with higher doping concentration in the drain region was desirable for the 1T-DRAM using bipolar junction mode.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.213.2-213.2
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• 2015

모바일 기기의 성장세로 인해 낸드 플래시 메모리에 대한 수요가 급격히 증가하면서 높은 집적도의 소자에 대한 요구가 커지고 있다. 그러나 기존의 MOSFET 구조의 소자는 비례 축소에 의한 게이트 누설 전류, 셀간 간섭, 단 채널 효과 같은 여러 어려움에 직면해 있다. 특히 트윈 실리콘 나노 와이어 전계 효과 트랜지스터 (TSNWFETs)는 소자의 크기를 줄이기 쉬우며 게이트 비례 축소가 용이하여 차세대 메모리 소자로 각광받고 있다. 그러나 TSNWFETs의 공정 방법과 실험적인 전기적 특성에 대한 연구는 많이 이루어 졌지만, TSNWFETs의 전기적 특성에 대한 이론적인 연구는 많이 진행되지 않았다. 본 연구는 직경의 크기가 다른 나노 와이어를 사용한 TSNWFETs의 전기적 특성에 대해 이론적으로 계산하였다. TSNWFETs과 실리콘 나노 와이어를 사용하지 않은 전계 효과 트랜지스터(FET)를 3차원 시뮬레이션 툴을 이용하여 계산하였다. TSNWFETs와 FETs의 드레인 전류와 문턱전압 이하 기울기, 드레인에 유기된 장벽의 감소 값, 게이트에 유기된 드레인 누설 전류 값을 이용하여 전류-전압 특성을 계산하였다. 이론적인 결과를 분석하여 TSNWFETs의 스위칭 특성과 단 채널 효과를 최소화하는 특성 및 전류 밀도를 볼 수 있었으며, 나노 와이어의 직경이 감소하면 증가하는 드레인에 유기된 장벽의 감소를 볼 수 있었다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.773-776
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• 2014

In this work, analog performances of silicon nanowire MOSFET with different length and channel width have been measured. The channel widths are 20nm, 30nm, 80nm, 130nm and lengths are 250nm, 300nm, 350nm, 500nm. temperatures $30^{\circ}C$, $50^{\circ}C$, $75^{\circ}C$, $100^{\circ}C$ have been measured. The trans-conductance, early voltage, gain, drain current and mobility have been characterized as a function of temperature. The mobility has been enhanced with wider channel width but it has been reduced with longer length and higher temperature. The trans-conductance has been increased with wider channel width. The early voltage has been enhanced with increase of gate length and temperature but it has been reduced with wider width. Therefore, gain has been enhanced with increase of gate longer length and wider width but it has been reduced with higher temperature.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.879-882
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• 2015

In this work, we have analyzed the characteristics of vertical nanowire GAA MOSFET according to channel width and the type of channel doping through the simulation. First, we compared and analyzed the characteristics of designed structures which have tilted shapes that ends of drains are fixed as 20nm and ends of sources are 30nm, 50nm, 80nm and 110nm. Second, we designed the rectangular structure which has uniform width of drain, channel and source as 50nm. We used it as a standard and designed trapezoidal structure which is tilted so that the end of drain became 20nm and reverse trapezoidal structure which is tilted so that the end of source became 20nm. We compared and analyzed the characteristic of above three structures. For the last, we used the rectangular structure, divided its channel as five parts and changed the type of the five parts of doping concentration variously. In the first simulation, when the channel width is the shortest, in the second, when the structure is trapezoid, in the third, when the center of channel is high doped show the best characteristics.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.889-893
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• 2015

In this work, the characteristics of GIDL current in nanowire GAA MOSFET with different channel width and hot carrier stress. When the gate length is fixed as a 250nm the GIDL current with different channel width of 10nm, 50nm, 80nm, and 130nm have been measured and analyzed. From the measurement, the GIDL is increased as the channel width decreaes. However, the derive current is increased as the channel width increases. From measurement results after hot carrier stress, the variation of GIDL current is increased with decreasing channel width. Finally, the reasons for the increase of GIDL current with decreasing channel width and r device. according to hot carrier stress GIDL's variation shows big change when width and the increase of GIDL current after hot carrier stress are confirmed through the device simulation.

• Journal of Sensor Science and Technology
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• v.15 no.1
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• pp.1-6
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• 2006

We fabricated Si nano-wire MOSFET by using the conventional photolithography with a $1.5{\mu}m$ resolution. Si nano-wire was fabricated by using reactive ion etching (RIE), anisotropic wet etching and thermal oxidation on a silicon-on-insulator (SOI) substrate, and its width is 30 nm. Logarithmic circuit consisting of a NMOSFET and Si nano-wire MOSFET has been constructed for application to high-sensitivity image sensor. Its sensitivity was 1.12 mV/lux. The output voltage swing was 1.386 V.

• Proceeding of EDISON Challenge
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• 2016.03a
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• pp.357-361
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• 2016

Si와 InAs 두 가지 채널 물질을 가지고 3가지 수송 방향 <100>, <110>, <111>으로 변화시키며 각각의 Nanowire nMOSFETs을 가지고 ballistic quantum transport simulation을 진행하였다. 각각의 경우에 대해 E-k curve를 구한 다음에 band curvature로 캐리어의 유효질량을 계산하고, 이를 통해 MOSFET의 전류 세기를 결정짓는 DOS와 carrier injection velocity를 구하여 어떤 경우에 가장 높은 ON-current를 흐르게 하는지 확인해 보았다. 하지만 예상과 달리 나노와이어의 직경이 1.4nm으로 매우 작기 때문에 valley-splitting이 일어나 Si<110>의 경우에 가장 작은 캐리어 유효 질량을 갖고 있는 사실을 확인할 수 있었다. 결론적으로 Si<100>의 경우에 trade-off 관계에 있는 DOS와 carrier injection velocity가 6가지 경우 중 최적의 조합을 가짐으로써 가장 높은 ON-current를 흐르게 하였다.