• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.6
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• pp.1-9
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• 2010

In this paper, we propose a hi-speed/low-power Extended QRD-RLS(QR-Decomposition Recursive Least Squares) equalizer with systolic array structure. In the conventional systolic array structure, vector mode CORDIC on the boundary cell calculates angle of input vector, and the rotation mode CORDIC on the internal cell rotates vector. But, in the proposed structure, it is shown that implementation complexity can be reduced using the rotation direction of vector mode CORDIC and rotation mode CORDIC. Furthermore, calculation time can be reduced by 1/2 since vector mode and rotation mode CORDIC operate at the same time. Through HDL coding and chip implementation, it is shown that implementation area is reduced by 23.8% compared with one of conventional structure.

• Proceedings of the Korean Information Science Society Conference
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• 2010.06d
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• pp.432-435
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• 2010

네트워크 기기분야에서는 정보통신기기 및 고속 멀티미디어 데이터 수요의 증가에 따라 네트워크 기기의 전력소비가 꾸준히 증가하고 있다. 특히 홈 네트워크 기기들은 전원이 연결되어 있는 상태로 동작하여 데이터 통신이 발생하지 않는 상황에서도 일정한 전력소모가 발생하므로 이에 대한 대처기술이 마련되어야 한다. 본 논문에서 대기전력 지원 홈게이트웨이 시스템 구현을 위하여 하드웨어를 설계하고 저전력 대기모드 지원 네트워크 프로토콜 인터페이스 개발하였으며 홈게이트웨이 시뮬레이터 S/W를 개발하여 홈게이트웨이의 기능을 시험테스트 하였다. 시뮬레이터 시험결과 각 네트워크 포트에서 발생된 트래픽에 따라 홈게이트웨이의 전원 모드가 변경됨을 확인할 수 있었으며 대기모드 시 소모 전력이 1W 미안으로 측정되었다.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.7
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• pp.659-664
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• 2016

In this paper, we suggest operational trans-conductance amplifier(OTA) for current-mode FIR filter that can be used in a digital circuit system requiring high operating frequency and low power consumption. The current-mode signal processing is one of the very innovative design method for a low power consumption system with high operating frequency because it shows a constant power regardless of frequency. From the simulation result using 0.35um CMOS process, when Vdd is 2V, it is confirmed that the proposed circuit showed the dynamic range of the about 1V, about 50% of supply voltage and output current swing of about 0~200uA. Also, the power consumption was evaluated with about 21uW and the active size for an integration was measured with $71um{\times}166um$.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.7 no.1
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• pp.33-44
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• 1997

BISDN(Broadband Integrated Service Digital Network)의 AAL-1(ATM Adaptation Layer-1)에서는 오류정정능력이 2인 (128,124) RS(Reed Slomon) 부호를 이용하여 ATM 셀에서 발생하는 오류를 정정하고 있다. 본 논문에서는 기존의 RS 복호 알고리즘을 분석한 후, 이를 바탕으로 AAL-1 기본오류정정 모드에 적용 가능한 복잡도가 낮고 고속 동작이 가능한 복호 알고리즘을 제시하고, 부호기와 보호기를 VHDL로 부호화하고 설계한 후, 관련 회로를 시뮬레이션한다. 또한 시뮬레이션된 회로를 XACT을 이용하여 XC 4025 FPGA에 실현하여 제안되 복호 알고리즘의 타당성을 확인한다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.135-144
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• 2003

This work proposes on-chip full CMOS current and voltage references for high-speed mixed-mode circuits. The proposed current reference circuit uses a digital-domain calibration method instead of a conventional analog calibration to obtain accurate current values. The proposed voltage reference employs internal reference voltage drivers to minimize the high-frequency noise from the output stages of high-speed mixed-mode circuits. The reference voltage drivers adopt low power op amps and small- sized on-chip capacitors for low power consumption and small chip area. The proposed references are designed, laid out, and fabricated in a 0.18 um n-well CMOS process and the active chip area is 250 um x 200 um. The measured results show the reference circuits have the power supply variation of 2.59 %/V and the temperature coefficient of 48 ppm/$^{\circ}C$ E.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.5
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• pp.35-41
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• 2008

This paper presents the design method of current-mode signal processing for high speed and low power digital audio signal processing. The digital audio processor requires a digital signal processing such as fast Fourier transform (FFT), which has a problem of large power consumption according to the settled point number and high speed operation. Therefore, a current-mode signal processing with a switched Current (SI) circuit was employed to the digital audio signal processing because a limited battery life should be considered for a low power operation. However, current memory that construct a SI circuit has a problem called clock-feedthrough. In this paper, we examine the connection of dummy MOS that is the common solution of clock-feedthrough and are willing to calculate the relation of width between dummy MOS for a proposal of the design methodology for improvement of current memory. As a result of simulation, in case of that the width of memory MOS is 20um, ratio of input current and bias current is 0.3, the relation of width between switch MOS and dummy MOS is $W_{M4}=1.95W_{M3}+1.2$ for the width of switch MOS is 2~5um, it is $W_{M4}=0.92W_{M3}+6.3$ for the width of switch MOS is 5~10um. Then the defined relation of MOS transistors can be a useful design guidance for a high speed low power digital audio processor.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.357-360
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• 2013

A 1.8V 2-Gb/s scalable low voltage signaling (SLVS) transmitter (TX) is designed for mobile applications requiring high speed and low power consumption. It consists of 4-lane TX for data transmission, 1-lane TX for a source synchronous clocking, and a 8-phase clock generator. The proposed SLVS TX has the scaling voltage swing from 50 mV to 650 mV and supports a high speed (HS) mode and a low power (LP) mode. An output impedance calibration scheme for the SVLS TX is proposed to improve the signal integrity. The proposed SLVS TX is implemented by using a $0.18-{\mu}m$ 1-poly 6-metal CMOS with a 1.8V supply. The simulated data jitter of the implemented SLVS TX is about 8.04 ps at the data rate of 2-Gbps. The area and power consumption of the 1-lane of the proposed SLVS TX are $422{\times}474{\mu}m^2$ and 5.35 mW/Gb/s, respectively.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.10
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• pp.27-33
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• 1998

In this paper, we designed a demodulator using proposed synchronization techniques and algorithms for high-speed ATM satellite burst modem, and analyzed various performance in the AWGN channel. In addition, as the preamble progressed, each synchronization process can be analyzed by using the mean and variance characteristics, and the convergence state and operation state using convergence probability can also be determined. In conclusion, we analyzed the Cell Loss Ratio(CLR) by integrating the burst acquisition with Unique Word(UW) detector performance, and verified that proposed TDMA receiver satisfied the generally required CLR performance adequately.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.291-292
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• 2014

High-speed video transmission modes of master bridge IC are implemented, which supports MIPI (Mobile Industry Processor Interface) DSI (Display Serial Interface) standard. MIPI DSI master bridge IC sends RGB data and various commands to display module (slave) in order to test it. The master bridge IC consists of buffers storing video data of two lines, packet generation block, and D-PHY layer that distributes packets to data lanes and transmits them to slave. In addition, it supports four bpp (bit per pixel) formats and three transmission modes including Burst and Non-Burst (Sync Events, Sync Pulses types). The designed bridge IC is verified by RTL simulations showing that it functions correctly for various operating parameters.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.455-456
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• 2019

본 논문은 태양광 발전시스템에서 일사량이 급변했을 때 최대 전력점(MPP: Maximum Power Point)을 빠르게 추종할 수 있는 P&O(Perturb and Observe)기반 가변 스텝 알고리즘을 제안하였다. 제안한 기법은 일사량 또는 온도에 의해 환경 변화 시 최대 전력점에서의 전압 변화 특성을 이용하며, 가변 스텝 방식이 적용된 전압제어를 통해 MPP를 추종한다. 임계값 설정으로 일사량 급변을 판단하며, MPP를 빠르게 추종하기 위한 고속 모드로 동작한다. MPP에 도달하면 가변 모드로 전환하여 정상상태 오차를 최소화 한다. PV 시뮬레이터와 태양광 전력변환시스템을 통해 제안한 MPPT 알고리즘의 성능을 검증하였다.