Journal of the Institute of Electronics Engineers of Korea TC (대한전자공학회논문지TC)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design and Implementation of Hi-speed/Low-power Extended QRD-RLS Equalizer using Systolic Array and CORDIC

시스톨릭 어레이 구조와 CORDIC을 사용한 고속/저전력 Extended QRD-RLS 등화기 설계 및 구현

  • 문대원 (상명대학교 컴퓨터정보통신공학과) ;
  • 장영범 (상명대학교 공과대학 정보통신공학과) ;
  • 조용훈 ((주)코메스타)
  • Received : 2009.08.31
  • Accepted : 2010.06.03
  • Published : 2010.06.25
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Abstract

In this paper, we propose a hi-speed/low-power Extended QRD-RLS(QR-Decomposition Recursive Least Squares) equalizer with systolic array structure. In the conventional systolic array structure, vector mode CORDIC on the boundary cell calculates angle of input vector, and the rotation mode CORDIC on the internal cell rotates vector. But, in the proposed structure, it is shown that implementation complexity can be reduced using the rotation direction of vector mode CORDIC and rotation mode CORDIC. Furthermore, calculation time can be reduced by 1/2 since vector mode and rotation mode CORDIC operate at the same time. Through HDL coding and chip implementation, it is shown that implementation area is reduced by 23.8% compared with one of conventional structure.

이 논문에서는 시스톨릭 어레이 구조를 갖는 고속/저전력 Extended QRD-RLS 등화기 구조를 제안한다. 기존의 시스톨릭 어레이 구조를 갖는 Extended QRD-RLS 등화기는 입력행렬의 QR분해를 위해서 벡터모드 CORDIC을 사용하여 벡터의 각도를 계산하고, 회전모드 CORDIC에서는 이 각도를 전달받아 벡터를 회전시킨다. 제안된 등화기 구조에서는 벡터모드 CORDIC과 회전모드 CORDIC이 정반대방향으로 회전하는 것을 이용하여 구현 하드웨어의 크기를 현저히 감소시켰다. 이와 더불어 제안구조에서는 벡터모드 CORDIC과 회전모드 CORDIC을 동시에 동작함으로써 계산시간을 1/2로 감소시킬 수 있었다. 제안구조의 HDL 코딩과 칩 설계를 통하여 기존의 시스톨릭 어레이 구조와 비교하여 23.8%의 구현면적 감소를 확인하였다.

Keywords

References

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