• Title/Summary/Keyword: 경계스캔 설계

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A Design of Flag Based Wrapped Core Linking Module for Hierarchical SoC Test Access (계층적 SoC테스트 접근을 위한 플래그 기반 코아 연결 모듈의 설계)

  • 송재훈;박성주;전창호
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.1
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    • pp.52-60
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    • 2003
  • For a System-on-a-Chip(SoC) comprised of multiple IP cores, various design techniques have been proposed to provide diverse test link configurations. In this paper, we introduce a new flag based Wrapped Core Linking Module (WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cores and P1500 wrapped cores with requiring least amount of area overhead compared with other state-of-art techniques. The design preserves compatibility with standards and scalability for hierarchical access.

A Design of FPGA Self-test Circuit Reusing FPGA Boundary Scan Chain (FPGA 경계 스캔 체인을 재활용한 FPGA 자가 테스트 회로 설계)

  • Yoon, Hyunsik;Kang, Taegeun;Yi, Hyunbean
    • Journal of the Institute of Electronics and Information Engineers
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    • v.52 no.6
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    • pp.70-76
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    • 2015
  • This paper introduces an FPGA self-test architecture reusing FPGA boundary scan chain as self-test circuits. An FPGA boundary scan cell is two or three times bigger than a normal boundary scan cell because it is used for configuring the function of input/output pins functions as well as testing and debugging. Accordingly, we analyze the architecture of an FPGA boundary scan cell in detail and design a set of built-in self-test (BIST) circuits in which FPGA boundary scan chain and a small amount of FPGA logic elements. By reusing FPGA boundary scan chain for self-test, we can reduce area overhead and perform a processor based on-board FPGA testing/monitoring. Experimental results show the area overhead comparison and simulation results.

Scan Design Techniques for Chip and Board Level Testability (디지탈 IC 및 보드의 시험을 위한 스캔 설계기술)

  • 민형복
    • The Magazine of the IEIE
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    • v.22 no.12
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    • pp.93-104
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    • 1995
  • 디지탈 회로를 구현한 칩 및 보드의 시험 비용을 줄이기 위하여 사용되는 스캔 설계 기술 동향에 대하여 기술하였다. 스캔 설계 기술은 칩 수준에서 먼저 적용되기 시작하였다. 회로의 모든 플립플롭을 스캔할 수 있도록 하는 완전 스캔이 먼저 개발되었고, 최근에는 플립플롭의 일부분만 스캔할 수 있도록 하는 부분 스캔 기술이 활발하게 논의되고 있다. 한편 보드의 시험에 있어서도 보드에 실장되는 칩의 밀도가 증가되고, 표면 실장 기술이 일반화됨에 따라 종래의 시험 기술로는 충분한 시험을 거치는 것이 불가능하게 되었다. 따라서, 칩에 적용되던 기법과 유사한 스캔 설계 기술이 적용되기 시작하였다. 이를 경계 스캔(Boundary Scan)이라고 하는데, 이 기술은 80년대 후반부터 본격적으로 논의되기 시작하였다. 1990년에는 이 기술과 관련된 IEEE의 표준이 제정되어 더욱 많이 적용되는 추세에 있다. 이 논문에서는 이러한 칩 및 보드의 시험을 쉽게하기 위한 스캔 설계 기법의 배경, 발전 과정 및 기술의 내용을 소개한다.

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Development of Continuous Capture Test Architecture in the Boundary Scan (경계면스캔에서의 연속캡쳐 시험구조 개발)

  • Jhang, Young-Sig;Lee, Chang-Hee
    • The KIPS Transactions:PartA
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    • v.16A no.2
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    • pp.79-88
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    • 2009
  • In boundary scan architecture, test stimuli are shifted in one at a time and applied to the on-chip system logic. The test results are captured into the BSR and are examined by subsequent shifting. In this paper, we developed a continuous capture test architecture and test procedure using TPG based on boundary scan is used to performance test. In this architecture, test patterns of TPG are applied to CUT with system clock rate, and response of CUT is continuously captured by CBSR(Continuous Capture Boundary Scan Register) at the same rate and the captured results is shifted to TDO at the same rate. The suggested a continuous capture test architecture and test procedure is simulated by Altera Max+Plus 10.0. The simulation results shows the accurate operation and effectiveness of the proposed test architecture and procedure.

Development of selectable observation point test architecture in the Boundry Scan (경계면스캔에서의 선택가능한 관측점 시험구조의 개발)

  • Lee, Chang-Hee;Jhang, Young-Sig
    • Journal of the Korea Society of Computer and Information
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    • v.13 no.4
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    • pp.87-95
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    • 2008
  • In this paper, we developed a selectable observation Point test architecture and test procedure for clocked 4-bit synchronous counter circuit based on boundary scan architecture. To develope, we analyze the operation of Sample/Preload instruction on boundary scan architecture. The Sample/Preload instruction make Possible to snapshot of outputs of CUT(circuit under test) at the specific time. But the changes of output of CUT during normal operation are not possible to observe using Sample/Preload in typical scan architecture. We suggested a selectable observation point test architecture that allows to select output of CUT and to observe of the changes of selected output of CUT during normal operation. The suggested a selectable observation point test architecture and test procedure is simulated by Altera Max 10.0. The simulation results of 4-bit counter shows the accurate operation and effectiveness of the proposed test architecture and procedure.

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A Design of Instruction Based Wrapped Core Linking Module for Hierarchical SoC Test Access (계층적 SoC 테스트 접근을 위한 명령어 기반 코아 연결 모듈의 설계)

  • Yi Hyun-Bean;Park Sung-Ju
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.52 no.3
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    • pp.156-162
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    • 2003
  • For a System-on-a-Chip(SoC) comprised of multiple IP cores, various design techniques have been proposed to provide diverse test link configurations. In this paper, we introduce a new instruction based Wrapped Core Linking Module(WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cotes and P1500 wrapped cores with requiring least amount of area overhead compared with other state-of-art techniques. The design preserves compatibility with standards and scalability for hierarchical access.

Important Facility Guard System Using Edge Computing for LiDAR (LiDAR용 엣지 컴퓨팅을 활용한 중요시설 경계 시스템)

  • Jo, Eun-Kyung;Lee, Eun-Seok;Shin, Byeong-Seok
    • KIPS Transactions on Computer and Communication Systems
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    • v.11 no.10
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    • pp.345-352
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    • 2022
  • Recent LiDAR(Light Detection And Ranging) sensor is used for scanning object around in real-time. This sensor can detect movement of the object and how it has changed. As the production cost of the sensors has been decreased, LiDAR begins to be used for various industries such as facility guard, smart city and self-driving car. However, LiDAR has a large input data size due to its real-time scanning process. So another way for processing a large amount of data are needed in LiDAR system because it can cause a bottleneck. This paper proposes edge computing to compress massive point cloud for processing quickly. Since laser's reflection range of LiDAR sensor is limited, multiple LiDAR should be used to scan a large area. In this reason multiple LiDAR sensor's data should be processed at once to detect or recognize object in real-time. Edge computer compress point cloud efficiently to accelerate data processing and decompress every data in the main cloud in real-time. In this way user can control LiDAR sensor in the main system without any bottleneck. The system we suggest solves the bottleneck which was problem on the cloud based method by applying edge computing service.

Fault Models and Diagonousis of Boundary Scan Board (경계스캔이 적용된 보드에서의 고장 모델 및 전단 기법)

  • Moon, Kweon-Woo;Song, Oh-Young
    • Proceedings of the Korea Information Processing Society Conference
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    • 2002.04b
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    • pp.1619-1622
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    • 2002
  • 최근에 생산되는 디지털 VLSI칩들은 그 집적도가 계속 높아지고 있으며, 이러한 칩들을 장착한 보드의 경우도 그 복잡성이 점차 높아지고 있다. 이에 따라 칩 및 보드에 대한 철저한 테스트 과정이 요구된다. 지금까지 보드 테스트 방법으로 널리 쓰였던 ICT(In-Circuit Test)는 칩의 고집적화에 따른 핀 간격의 조밀화와 SMT(Surface Mount Technology), BGA(Ball Grid Array), MCM(Multi Chip Module) 등의 새로운 패키징 방식의 등장에 따라 테스트 방법으로의 한계성을 드러내고 있다. 이에 대한 대안으로 등장한 IEEE Std 1149.1 은 ICT의 한계성을 극복할 수 있는 기술일 뿐 아니라 여러 가지 장점을 가지고 있으며 그 활용 분야도 다양하다. 본 논문에서는 IEEE Std 1149.1에 따라 설계된 보드 상에서 발생 가능한 고장들에 대한 고장 모델을 제시한다. 또한 각 고장 모델들의 양상과 진단 기법을 제시한다. 이를 통해 IEEE Std 1149.1에 따라 설계된 보드 상에서 발생한 고장들을 검출할 수 있으며, 고장의 종류 및 성격, 그리고 고장의 발생 위치 등의 정보를 얻을 수 있다. IEEE Std 1149.1에 따른 보드 설계가 보드의 신뢰성 보장에 긴요함을 인식하는 계기가 되기를 기대하며 제시된 고장 모델 및 진단 기법이 기술적으로 중요한 참고자료가 되기를 기대한다.

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VLSI Architecture Design of Reconstruction Filter for Morphological Image Segmentation (형태학적 영상 분할을 위한 재구성 필터의 VLSI 구조 설계)

  • Lee, Sang-Yeol;Chung, Eui-Yoon;Lee, Ho-Young;Kim, Hee-Soo;Ha, Yeong-Ho
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.36S no.12
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    • pp.41-50
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    • 1999
  • In this paper, the new VLSI architecture of a reconstruction filter for morphological image segmentation is proposed. The filter, based on the $h_{max}$ operation, simplifies the interior of each region while preserving the boundary information. The proposed architecture adopts a partitioned memory structure and an efficient image scanning strategy to reduce the operations. The proposed memory partitioning scheme makes it possible that every data required for processing can be read from each memory at a time, resulting in parallel data processing. By the extended connectivity consideration, the operation is much decreased because more simplification is achieved in scanning stage. The selective raster scan strategy endows the satisfactory noise removal capability with negligible hardware complexity increase. The proposed architecture is designed using VHDL, and functional evaluation is performed by the CAD tool, Mentor. The experiment results show that the proposed architecture can simplify image profile with less than 18% operations of the conventional method.

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Test Methodology for Multiple Clocks Single Capture Scan Design based on JTAG IEEE1149.1 Standard (IEEE 1149.1 표준에 근거한 다중 클럭을 이용한 단일 캡쳐 스캔 설계에 적용되는 경계 주사 테스트 기법에 관한 연구)

  • Kim, In-Soo;Min, Hyoung-Bok
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.56 no.5
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    • pp.980-986
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    • 2007
  • Boundary scan test structure(JTAG IEEE 1149.1 standard) that supports an internal scan chain is generally being used to test CUT(circuit under test). Since the internal scan chain can only have a single scan-in port and a single scan-out port; however, existing boundary test methods can not be used when multiple scan chains are present in CUT. Those chains must be stitched to form a single scan chain as shown in this paper. We propose an efficient boundary scan test structure that adds a circuit called Clock Group Register(CGR) for multiple clocks testing within the design of multiple scan chains. The proposed CGR has the function of grouping clocks. By adding CGR to a previously existing boundary scan design, the design is modified. This revised scan design overcomes the limitation of supporting a single scan-in port and out port, and it bolsters multiple scan-in ports and out ports. Through our experiments, the effectiveness of CGR is proved. With this, it is possible to test more complicated designs that have high density with a little effort. Furthermore, it will also benefit in designing those complicated circuits.