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http://dx.doi.org/10.5573/ieie.2015.52.6.070

A Design of FPGA Self-test Circuit Reusing FPGA Boundary Scan Chain  

Yoon, Hyunsik (Department of Computer Engineering, Hanbat National University)
Kang, Taegeun (Department of Computer Engineering, Hanbat National University)
Yi, Hyunbean (Department of Computer Engineering, Hanbat National University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.52, no.6, 2015 , pp. 70-76 More about this Journal
Abstract
This paper introduces an FPGA self-test architecture reusing FPGA boundary scan chain as self-test circuits. An FPGA boundary scan cell is two or three times bigger than a normal boundary scan cell because it is used for configuring the function of input/output pins functions as well as testing and debugging. Accordingly, we analyze the architecture of an FPGA boundary scan cell in detail and design a set of built-in self-test (BIST) circuits in which FPGA boundary scan chain and a small amount of FPGA logic elements. By reusing FPGA boundary scan chain for self-test, we can reduce area overhead and perform a processor based on-board FPGA testing/monitoring. Experimental results show the area overhead comparison and simulation results.
Keywords
FPGA; Built-in self test; BIST; Boundary-scan chain; IEEE 1149.1; I/O block;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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