• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.11
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• pp.1185-1191
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• 2014

An integrated ship area network has functionality of remote control and autonomous management of various sensors and instruments embedded or boarded in a ship. For such environment, a wireless bridge is essential to transmit control and/or managing information to sensors or instruments from a central integrated ship area network station. In this paper, one of reliable schemes of In-ship sensor networks using a Grid-based WPAN is proposed. The proposed scheme is based on a novel grid network which allows a multi-path communication, and is robust, energy efficient. The results demonstrate that the proposed Grid-based WPAN outperforms the IEEE 802.15.4 based network in terms of success ratio and power efficiency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2569-2578
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• 2009

Core-A microprocessor is the all-Korean product designed as 32-bit embedded RISC microprocessor developed by KAIST and supported by the Industrial Property Office. This paper analyze Core-A microprocessor architecture and proposes efficient method to interface Core-A microprocessor with coprocessor. To verify proposed interfacing method, the AES cryptography processor that has 128-bit key and block size is used as a coprocessor. Coprocessor and AES are written in Verilog-HDL and verified using Modelsim simulator. It except AES module consists of about 3,743 gates and its maximum operating frequency is about 90Mhz under 0.35um CMOS technology. The proposed coprocessor interface architecture is efficiency to send data or to receive data from Core-A to coprocessor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.3
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• pp.643-650
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• 2014

A hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is described. The designed phase calculator adopts redundant binary number systems and a pipelined architecture to improve throughput and speed. It performs arctangent operation using vectoring mode of DCORDIC(Differential COordinate Rotation DIgital Computer) algorithm. Fixed-point MATLAB simulations are carried out to determine the optimal bit-widths and number of iteration. The phase calculator has ben verified by FPGA-in-the-loop verification using MATLAB/Simulink. A test chip has been fabricated using a TSMC $0.18-{\mu}m$ CMOS process, and test results show that the chip functions correctly. It has 82,000 gates and the estimated throughput is 400 MS/s at 400Mhz@1.8V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.10
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• pp.2509-2515
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• 2014

In this paper, the conventional vertical structure for VLSI circuits CMOS intend to improve the stress effects of active region and built-in threshold voltage. For these improvement, the proposed structure is shallow trench isolation of moat shape. We want to analysis the electron concentration distribution, gate bias vs energy band, thermal stress and dielectric enhanced field of thermal damage between vertical structure and proposed moat shape. Physically based models are the ambient and stress bias conditions of TCAD tool. As an analysis results, shallow trench structure were intended to be electric functions of passive as device dimensions shrink, the electrical characteristics influence of proposed STI structures on the transistor applications become stronger the potential difference electric field and saturation threshold voltage, are decreased the stress effects of active region. The fabricated device of based on analysis results data were the almost same characteristics of simulation results data.

• Proceedings of the KIPE Conference
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• 2016.11a
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• pp.171-173
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• 2016

일반적으로 대형 버스 및 트럭 등 같은 경우, 부하가 아주 크다. 또한 내리막길이나 장거리 운행 시에 잦은 제동으로 인하여 마찰을 이용한 기존 방식의 브레이크들은 브레이크 파열 및 페이드 현상 때문에 제동 안전성에 문제가 있다. 이러한 제동 부담을 분담하기 위해 현재 보조브레이크(리타더)가 필수적이며, 엔진 계통의 보조브레이크가 아닌 비접촉식 브레이크 같은 친환경 보조브레이크가 요구되고 있다. 그리고 차량 제동시 발생하는 기계에너지를 전기에너지로 회생하여 에너지효율을 향상시키려는 연구가 현재 활발히 진행되고 있다. 본 논문에서는 와전류를 이용한 전자기형 리타더에서 발생되는 전기에너지를 회수하기 위한 전압 제어 방법을 다룰 것이다. 리타더의 제동에너지를 전기에너지로 회생하기 위해 L-C 공진회로로 구성하였다. 리타더를 자여자 유도발전기(Self-Excited Induction Generator)로 모델링 하였고 이를 토대로 시뮬레이션 및 실험을 진행하였다. 자여자 유도발전기의 구동 조건에 대해서 언급하고 이를 파라미터에 따라 3-D map으로 만들었다. 또 회로 중의 FET 게이트에 전압을 인가하는 제어장치의 구동펄스에 따라 바뀌는 공진회로의 전압을 분석하였으며, 이 전압을 제어하기 위하여 PI 제어기를 이용한 알고리즘을 제안하였다. 이 전압을 3상 AC/DC컨버터를 통과한 후 DC/DC컨버터를 통하여 차량 내부의 배터리에 충전되는데 제어를 위해 3상 AC/DC에서의 전압 리플을 MA(Moving Average) 방식의 필터를 사용하여 DC/DC컨버터의 입력에 맞도록 제어하였다. 이와 같이 전자기형 리타더에서 유도되는 전압을 제어기의 제어 펄스에 따라 제어할 수 있으며 Matlab Simulink를 이용하여 리타더의 모델과 그 제어기의 타당성을 보였다. 또 실제 M-G Set 실험을 통하여 그 연관성을 확인하였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.4
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• pp.56-61
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• 2015

Ideal and stretch-out C-V curve were shown at high frequency using SiGe p-FinFET simulation. Average interface trap density can be extracted by the difference of voltage axis on ideal and stretch-out C-V curve. Also, interface trap density(Dit) was extracted by Terman's method that uses the same stretch-out of C-V curve with interface trap characteristic, and average interface trap density was calculated at same energy level. Comparing the average interface trap density, which was found by method using difference of voltage, with Terman's method, it was verified that the two methods almost had the same average interface trap density.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.6
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• pp.1056-1063
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• 2008

This paper describes an efficient design of a multi-standard Viterbi decoder that supports multiple constraint lengths and code rates. The Viterbi decoder is parameterized for the code rates 1/2, 1/3 and constraint lengths 7,9, thus it has four operation nodes. In order to achieve low hardware complexity and low power, an efficient architecture based on hardware sharing techniques is devised. Also, the optimization of ACCS (Accumulate-Subtract) circuit for the one-point trace-back algorithm reduces its area by about 35% compared to the full parallel ACCS circuit. The parameterized Viterbi decoder core has 79,818 gates and 25,600 bits memory, and the estimated throughput is about 105 Mbps at 70 MHz clock frequency. Also, the simulation results for BER (Bit Error Rate) performance show that the Viterbi decoder has BER of $10^{-4}$ at $E_b/N_o$ of 3.6 dB when it operates with code rate 1/3 and constraints 7.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.4
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• pp.696-706
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• 2007

Multiprocessor system on chip (MPSoC) platform has set a new innovative trend for the System on Chip (SoC) design. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and un-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future SoC. Most future SoCs will use network architecture and a packet based communication protocol for on chip communication. This paper presents an adaptive wormhole routing with proactive turn prohibition to guarantee deadlock free on chip communication for NOC architecture. It shows a simple muting architecture with five full-duplex, flit-wide communication channels. We provide simulation results for message latency and compare results with those of dimension ordered techniques operating at the same link rates.

• Journal of Digital Convergence
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• v.16 no.12
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• pp.309-315
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• 2018

In this paper, propose an efficient arc detection and control method to achieve fast machining speed, improved precision and surface roughness in discharge machining, especially for carbide and hard material processing and metal processing using discharge phenomenon as energy. A single discharge waveform is divided into three sections of Td (Time-Delay), Ton (Time-on) and Toff (Time-off) and the gate control timing is simulated using the HDL language. In this paper, we analyze the effect of the gap between the electrode and the workpiece on the machining results by determining the operation of the servo mechanism by sampling the Td section through the comparator circuit. As a result of the analysis, the Td section of the formed waveform was more precisely sampled at a high speed and the results were improved when applied to the gap control between the electrode and the workpiece.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.5
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• pp.15-25
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• 2002

In this paper a design of high performance cryptographic processor which implements AES Rijndael algorithm is described. To eliminate performance degradation due to round-key computation delay of conventional processor, the on-the-fly precomputation of round key based on modified round structure is adopted. And on-the-fly round key generator which supports 128, 192, and 256-bit key has modular structure. The designed processor has iterative structure which uses 1 clock cycle per round and supports three operation modes, such as ECB, CBC, and CTR mode which is a candidate for new AES modes of operation. The cryptographic processor designed in Verilog-HDL and synthesized using 0.251$\mu\textrm{m}$ CMOS cell library consists of about 51,000 gates. Simulation results show that the critical path delay is about 7.5ns and it can operate up to 125Mhz clock frequency at 2.5V supply. Its peak performance is about 1.45Gbps encryption or decryption rate under 128-bit key ECB mode.