• Journal of the Korea Institute of Information and Communication Engineering
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• 제11권8호
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• pp.1558-1563
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• 2007

In this paper, phase-locked loop (PLL) of a combinational architecture consisting of an adaptive bandwidth and fractional-N is presented to improve performances and reduce the order of ${\Delta}{\Sigma}$ modulator while maintaining equivalent or better performance with fast locking. The architecture of adaptive bandwidth PLL was simulated by HSPICE using 0.35m CMOS parameters. The behavioral simulation of the proposed adaptive bandwidth fractional-N PLL with a ${\Delta}{\Sigma}$ modulator was carried out by using MatLab to determine if the architecture could achieve the objectives. The HSPICE simulation showed that this type of PLL was able to fast locking, and reduce fractional spurs about 20dB.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권2호
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• pp.170-183
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• 2013

This paper gives an overview of fractional-N phase-locked loops (PLLs) with practical design perspectives focusing on a ${\Delta}{\Sigma}$ modulation technique and a finite-impulse response (FIR) filtering method. Spur generation and nonlinearity issues in the ${\Delta}{\Sigma}$ fractional-N PLLs are discussed with simulation and hardware results. High-order ${\Delta}{\Sigma}$ modulation with FIR-embedded filtering is considered for low noise frequency generation. Also, various architectures of finite-modulo fractional-N PLLs are reviewed for alternative low cost design, and the FIR filtering technique is shown to be useful for spur reduction in the finite-modulo fractional-N PLL design.

• Journal of IKEEE
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• 제3권1호
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• pp.39-49
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• 1999

This paper describes a 1 GHz, low-phase-noise CMOS fractional-N frequency synthesizer with an integrated LC VCO. The proposed frequency synthesizer, which uses a high-order delta-sigma modulator to suppress the fractional spurious tones at all multiples of the fractional frequency resolution offset, has 64 programmable frequency channels with frequency resolution of $f_ref/64$. The measured phase noise is as low as -110 dBc/Hz at a 200 KHz offset frequency from a carrier frequency of 980 MHz. The reference sideband spurs are -73.5 dBc. The prototype is implemented in a $0.5{\mu}m$ CMOS process with triple metal layers. The active chip area is about $4mm^2$ and the prototype consumes 43 mW, including the VCO buffer power consumption, from a 3.3 V supply voltage.

• Journal of the Korean Mathematical Society
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• 제53권4호
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• pp.929-967
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• 2016

Let p(t, x) be the fundamental solution to the problem $${\partial}^{\alpha}_tu=-(-{\Delta})^{\beta}u,\;{\alpha}{\in}(0,2),\;{\beta}{\in}(0,{\infty})$$. If ${\alpha},{\beta}{\in}(0,1)$, then the kernel p(t, x) becomes the transition density of a Levy process delayed by an inverse subordinator. In this paper we provide the asymptotic behaviors and sharp upper bounds of p(t, x) and its space and time fractional derivatives $$D^n_x(-{\Delta}_x)^{\gamma}D^{\sigma}_tI^{\delta}_tp(t,x),\;{\forall}n{\in}{\mathbb{Z}}_+,\;{\gamma}{\in}[0,{\beta}],\;{\sigma},{\delta}{\in}[0,{\infty})$$, where $D^n_x$ x is a partial derivative of order n with respect to x, $(-{\Delta}_x)^{\gamma}$ is a fractional Laplace operator and $D^{\sigma}_t$ and $I^{\delta}_t$ are Riemann-Liouville fractional derivative and integral respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권1호
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• pp.41-48
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• 2002

This paper presents a 18-mW, 2.5-㎓ fractional-N frequency synthesizer with l-bit $4^{th}$-order interpolative delta-sigma ($\Delta{\;}$\sum$)modulator to suppress fractional spurious tones while reducing in-band phase noise. A fractional-N frequency synthesizer with a quadruple prescaler has been designed and implemented in a $0.5-\mu\textrm{m}$ 15-GHz $f_t$ BiCMOS. Synthesizing 2.1 GHzwith less than 200 Hz resolution, it exhibits an in-band phase noise of less than -85 dBc/Hz at 1 KHz offset frequency with a reference spur of -85 dBc and no fractional spurs. The synthesizer also shows phase noise of -139 dBc/Hz at an offset frequency of 1.2 MHz from a 2.1GHz center frequency.

• Proceedings of the KIEE Conference
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• 대한전기학회 2008년도 Techno-Fair 및 추계학술대회 논문집 전기물성,응용부문
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• pp.161-162
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• 2008

본 논문에서는 820.11n 규격에 적합한 Fractional-N 주파수 합성기를 설계하였다. 본 논문에서 설계한 주파수 합성기의 특징은 PFD(Phase Frequency Detector) 뒷단에 잔여 펄스를 제거하는 Pulse Remover를 연결하여 이중 궤환 Charge Pump의 안정도를 향상시켰으며, Charge Pump에서 동시에 발생하는 Up/Down 전류로 인한 Spike성 전류를 없앰으로서 스퓨리어스를 최소화 시켰다. Pulse Removed RFD를 사용함으로서 발생하는 PFD Deadzon문제는 2N+2분주와 2N-2분주기를 3차의 ${\Delta}{\Sigma}$ Modulator가 선택해줌으로 해결하였다. 삼성 0.18u 공정을 이용하여 설계 하였으며 각 블록은 Cadence spectre를 이용하여 검증하였다.

• Proceedings of the KIEE Conference
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.1386-1388
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• 2008

본 논문에서는 820.11n 규격에 적합한 Fractional-N 주파수 합성기를 설계하였다. 본 논문에서 설계한 주파수 합성기의 특징은 PFD(Phase Frequency Detector) 뒷단에 잔여 펄스를 제거하는 Pulse Remover를 연결하여 이중 궤환 Charge Pump의 안정도를 향상시켰으며, Charge Pump에서 동시에 발생하는 Up/Down 전류로 인한 Spike성 전류를 없앰으로서 스퓨리어스를 최소화 시켰다. Pulse Removed PFD를 사용함으로서 발생하는 PFD Deadzon문제는 2N+2분주와 2N-2분주기를 3차의 ${\Delta}{\Sigma}$ Modulator가 선택해줌으로 해결하였다. 삼성 0.18u 공정을 이용하여 설계 하였으며 각 블락은 Cadence spectre 를 이용하여 검증하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제43권10호
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• pp.90-96
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• 2006

A novel ${\Sigma}{\Delta}$ fractional-N PLL architecture for fast locking and fractional spur suppressing is proposed based on the capacitance scaling scheme. It changes the effective capacitance of loop filter (LF) by increasing and decreasing current to the capacitor via different paths with multiple charge pumps. The effective capacitance of loop filter (LF) can be scaled up/down depending on operating status while keeping LF capacitors small enough to be integrated into a single PLL chip. Fractional spurs suppressing have been achieved by reducing the magnitude of charge pump current when the PLL is in-lock without degrading fast locking characteristic. It has been simulated by HSPICE in a CMOS $0.35{\mu}m$ process, and shows flat locking time is less than $8{\mu}s$ with the small size of LF capacitors, 200pF and 17pF, and $2.8k{\Omega}$ resistor.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권3호
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• pp.179-192
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• 2008

A multiphase compensation method with mismatch linearization technique, is presented and demonstrated in a $\Sigma-\Delta$ fractional-N frequency synthesizer. An on-chip delay-locked loop (DLL) and a proposed delay line structure are constructed to provide multiphase compensation on $\Sigma-\Delta$ quantizetion noise. In the delay line structure, dynamic element matching (DEM) techniques are employed for mismatch linearization. The proposed $\Sigma-\Delta$ fractional-N frequency synthesizer is fabricated in a $0.18-{\mu}m$ CMOS technology with 2.14-GHz output frequency and 4-Hz resolution. The die size is 0.92 mm$\times$1.15 mm, and it consumes 27.2 mW. In-band phase noise of -82 dBc/Hz at 10 kHz offset and out-of-band phase noise of -103 dBc/Hz at 1 MHz offset are measured with a loop bandwidth of 200 kHz. The settling time is shorter than $25{\mu}s$.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.267-273
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• 2007

A fractional-N frequency synthesizer supports quadruple bands and multiple standards for mobile broadcasting systems. A novel linearized coarse tuned VCO adopting a pseudo-exponential capacitor bank structure is proposed to cover the wide bandwidth of 65%. The proposed technique successfully reduces the variations of KVCO and per-code frequency step by 3.2 and 2.7 times, respectively. For the divider and prescaler circuits, TSPC (true single-phase clock) logic is extensively utilized for high speed operation, low power consumption, and small silicon area. Implemented in $0.18-{\mu}m$ CMOS, the PLL covers $154{\sim}303$ MHz (VHF-III), $462{\sim}911$ MHz (UHF), and $1441{\sim}1887$ MHz (L1, L2) with two VCO's while dissipating 23 mA from 1.8 V supply. The integrated phase noise is 0.598 and 0.812 degree for the integer-N and fractional-N modes, respectively, at 750 MHz output frequency. The in-band noise at 10 kHz offset is -96 dBc/Hz for the integer-N mode and degraded only by 3 dB for the fractional-N mode.