Fractional-N Frequency Synthesis: Overview and Practical Aspects with FIR-Embedded Design |
Rhee, Woogeun
(Institute of Microelectronics, Tsinghua University)
Xu, Ni (Institute of Microelectronics, Tsinghua University) Zhou, Bo (Institute of Microelectronics, Tsinghua University, Beijing, China and now with Beijing Institute of Technology) Wang, Zhihua (Institute of Microelectronics, Tsinghua University) |
1 | G. C. Gillette, "The digiphase synthesizer," in Proceedings of 23rd Annual Frequency Control Symp., Apr. 1969, pp. 25-29. |
2 | J. Gibbs and R. Temple, "Frequency domain yields its data to phase-locked synthesizer," Electronics, pp. 107-113, Apr. 1978. |
3 | W. Rhee, "Design of low jitter 1-GHz phase-locked loops for digital clock generation," in Proc. IEEE ISCAS, May 1999, pp. 520-523. |
4 | V. Reinhardt, "Spur reduction techniques in direct digital synthesizers," in Proc. of 47th Frequency Control Symp., Oct. 1993, pp. 230-241. |
5 | M. Perrott, T. Tewksbury, and C. Sodini, "A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation," IEEE J. of Solid-State Circuits, vol. 32, pp. 2048-2060, Dec. 1997. DOI ScienceOn |
6 | S. Pamarti, L. Jansson, and I. Galton, "A wide-band 2.4GHz delta-sigma fractional-N PLL with 1-Mb/s in-loop modulation," IEEE J. Solid-State Circuits, vol. 39, pp. 49-62, Jan. 2004. DOI ScienceOn |
7 | R. Staszewski, et al., "All-digital PLL and transmitter for mobile phones," IEEE J. of Solid- State Circuits, vol. 40, pp. 2469-2482, Dec. 2005. DOI ScienceOn |
8 | T. A. Riley, M. Copeland, and T. Kwasniewski, "Delta-sigma modulation in fractional-N frequency synthesis," IEEE J. of Solid-State Circuits, vol. 28, pp. 553-559, May 1993. DOI ScienceOn |
9 | B. Miller and R. Conley, "A multiple modulator fractional divider," IEEE Trans. on Instrumentation and Measurement, vol. 40, pp. 578-583, June 1991. DOI ScienceOn |
10 | W. Rhee, B. Song, and A. Ali, "A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b thirdorder modulator," IEEE J. Solid-State Circuits, vol. 35, pp. 1453-1460, Oct. 2000. DOI ScienceOn |
11 | W. Rhee, "Practical design aspects in fractional-N frequency synthesis," Analog Circuit Design, Edited by A. van Roermund, M. Steyaert, and J. Huijsing, Springer Publishers, pp. 3-26, 2003. |
12 | B. De Muer and M. Steyaert, "On the analysis of fractional-N frequency synthesizers for highspectral purity," IEEE Trans. on Circuits and Systems II, vol. 50, pp. 784-793, Nov. 2003. DOI |
13 | H. Hedayati, B. Bakkaloglu, and W. Khalil, "Closed-loop nonlinear modeling of widebandfractional-N frequency synthesizers," IEEE Trans. Microw. Theory Tech., vol. 54, no. 10, pp. 3654-3663, Oct. 2006. DOI ScienceOn |
14 | P.-E. Su and S. Pamarti, "Fractional-N phaselocked-loop-based frequency synthesis: A tutorial," IEEE Trans. On Circuits and Systems II, vol. 56, no. 12, pp. 881-885, Dec. 2009. DOI ScienceOn |
15 | M. H. Perrott et al., "A low area, switched-resistor based fractional-N synthesizer applied to a MEMSbased programmable oscillator," IEEE J. Solid- State Circuits, vol. 45, pp. 2566-2581, Dec. 2010. DOI ScienceOn |
16 | K. Wahee, R. B. Staszewski, F. Dulger, M. S. Ullah, S. D. Vamvakos, "Spurious-free time-to-digital conversion in an ADPLL using short dithering sequences," IEEE Trans. on Circuits and Systems I, vol. 58, pp. 2051-2060, Sept. 2011. DOI ScienceOn |
17 | J. P. Hein and J. W. Scott, "z-domain model for discrete-time PLL's," IEEE Trans. Circuits Syst., vol. 35, pp. 1393-1400, Nov. 1988. DOI ScienceOn |
18 | P. V. Brennan, P. M. Radmore, and D. Jiang, "Intermodulation-borne fractional-N frequency synthesizer spurious components," IEE Circuits and Systems, vol. 151, pp. 536-542, Dec. 2004. |
19 | W. Rhee, K. Jenkins, J. Liobe, and H. Ainspan, "Experimental analysis of substrate noise effect on PLL performance," IEEE Trans. on Circuits and Systems II, vol. 55, pp. 638-642, July 2008. DOI ScienceOn |
20 | M. Gupta and B. Song, "A 1.8GHz spur cancelled fractional-N frequency synthesizer with LMSbased DAC gain calibration", IEEE J. Solid-State Circuits, vol. 41, pp. 2842-2851, Dec. 2006. DOI ScienceOn |
21 | S. E. Meninger and M. H. Perrott, "A 1MHz bandwidth 3.6GHz CMOS fractional-N synthesizer," IEEE J. of Solid-State Circuits, vol. 41, pp. 966-980, Apr. 2006. DOI ScienceOn |
22 | X. Yu, Y. Sun, W. Rhee, and Z. Wang, "An FIRembedded noise filtering method for fractional- N PLL clock generators," IEEE Journal of Solid-State Circuits, vol. 44, pp. 2426-2436, Sept. 2009. DOI ScienceOn |
23 | X. Yu, Y. Sun, W. Rhee, H. Ahn, B. Park, and Z. Wang, "A fractional-N frequency synthesizer with customized noise shaping for WCDMA/HSDPA applications," IEEE J. of Solid- State Circuits, vol. 44, pp. 2193-2201, Aug. 2009. DOI ScienceOn |
24 | X. Yu, et al., "A 65nm CMOS 3.6GHz fractional-N PLL with 5th-order delta-sigma modulation and weighted FIR Filtering," in Proc. IEEE A-SSCC, Nov. 2009, pp. 77-80. |
25 | W. Rhee and A. Ali, "An on-chip phasecompensation technique in fractional-N frequency synthesis," in IEEE ISCAS Proc., vol. 3, May 1999, pp. 363-366. |
26 | M. Kondoul, A. Matsuda, H. Yamazaki, and O. Kobayashi, "A 90-to-770MHz fractional-N synthesizer for a digital TV tuner," in IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp. 248-249. |
27 | D.-W. Jee, Y. Suh, H.-J. Park, and J.-Y. Sim, "A 0.1-fref BW 1GHz fractional-N PLL with FIR embedded phase-interpolator-based noise filtering," in IEEE ISSCC Dig. Tech. Papers, Feb. 2011, pp. 94-95. |
28 | I.-T. Lee, H.-Y. Lu, and S.-I. Liu, "A 6-GHz alldigital fractional-N frequency synthesizer using FIR-embedded noise filtering technique," IEEE Trans. on Circuits and Systems II, vol. 59, pp. 267-271, May 2012. DOI ScienceOn |
29 | C.-H. Park, O. Kim, and B. Kim, "A 1.8-GHz selfcalibrated phase locked loop with precise I/Q matching," IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 777-786, May 2001. DOI ScienceOn |
30 | S. Pamarti and S. Delshadpour, "A spur elimination technique for phase interpolation-based fractional- N PLLs," IEEE Trans. on Circuits Systems I, vol. 55, no. 6, pp. 1639-1647, Jul. 2008. DOI ScienceOn |
31 | L. Zhang, et al., "A hybrid spur compensation technique for finite-modulo fractional-N phaselocked loops," in IEEE J. of Solid-State Circuits, pp. 2922-2934, Nov. 2009. |
32 | B. Chi, X. Yu, W. Rhee, and Z. Wang, "A fractional-N PLL for digital clock generation with an FIR-embedded frequency divider," in Proc.IEEE ISCAS, pp. 3051-3054, May 2007. |
33 | B. Zhou, et al., "A 1Mb/s 3.2-4.4GHz reconfigurable FM-UWB transmitter in CMOS," in Proc. IEEE RFIC, June 2011, pp. 1-4. |