• 대한조선학회 특별논문집
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• 대한조선학회 2013년도 특별논문집
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• pp.73-80
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• 2013

From broad point of view, seam tracking has been one of main issues with respect to welding automation. Several attempts have been successful for seam tracking of fixed weaving width. As a solution of the seam tracking methods for varying groove width, the visual sensors such as CCD cameras have been adopted. Although the vision sensing techniques can achieve high accuracy, the weak point is that well-prepared vision sensor environment should be required to obtain high-quality visual measurements which can be easily affected by significant noises in industrial areas. This paper proposed an alternative seam tracking algorithm for narrow groove. A special measurement device for arc voltage, in this study, is developed to enhance the reliability of the measured welding signals. Based on the developed arc sensor algorithm, an automatic weld-width tracking algorithm is also proposed, which is able to predict the weld-position more accurately. The usefulness of the automatic weld-width tracking algorithm was well verified by applying it to gas tungsten arc welding (GTAW).

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.2753-2758
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• 2003

Tactile sensation is essential for many manipulation and exploration tasks not only in a real environment but also in a virtual environment. In this paper, we discuss a conceptual design of an integrated tactile display system. The system comprises two parts: a 2 DOF force feedback device for kinesthetic display and a tactile feedback device for displaying the normal stimulation to skin and the skin slip/stretch. Psychophysical experiments measure the effects of fingerpad selection, the direction of finger movements and the texture width on tactile sensitivity. We also investigate characteristics of lateral finger movement while subjects perceive different textures. From the experimental results, the principal parameters for designing a tactile display are suggested. A tactile display device is implemented using eight piezoelectric bimorphs and a linear actuator, and is attached to a 2 DOF translational force feedback device to simultaneously simulate texture and stiffness of the object.

• 마이크로전자및패키징학회지
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• 제27권1호
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• pp.31-35
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• 2020

원자층 증착법(ALD: atomic layer deposition)으로 성장된 ZnO n-type 산화물반도체를 이용하여 three terminal memristor (memtransistor) 소자를 제작하여 습도에 따른 그 특성을 관찰하였다. 40 nm 두께의 ZnO 박막을 이용하여 channel width 70 ㎛, length 5 ㎛, back gate 구조의 memtransistor 소자를 제작하여 습도에 (40%, 50%, 60%, 70%) 따른 gate tunable memristive 특성변화를 관찰하였다. 습도가 높아질수록 electron mobility와 gate controllability가 감소하여 수소도핑효과에 의한 carrier 농도가 증가하는 거동의 output curve가 관찰되었다. 60%, 70%의 습도에서 memristive 거동이 관찰되었으며 습도가 높아질수록 on/off ratio는 증가하는 반면 gate controllability가 감소하였다. 60% 습도에서 가장 우수한 특성의 gate tunable memristive 특성을 얻을 수 있었다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2000년도 전력전자학술대회 논문집
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• pp.605-609
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• 2000

This paper presents a development of the Pulse Width Modulation ASIC for control of the AC servo or spindle motor in machine tools. The ASIC is designed two PWM functions for simultaneous control of a converter and an inverter. Also the device includes additionally two UART functions for interfacing the RS232C with PC or other devices. The device is connected to the microprocessor of Intel or Motorola by bus interface. The required output voltage and frequency for the motor control is programmed to the PWM block and the corresponding switching signals are calculated and generated with regard to the programmed value.

• 한국전기전자재료학회논문지
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• 제22권7호
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• pp.555-558
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• 2009

This paper presents a step-down converter IC for automotive applications. This device was designed for a 40 V/1 A high-power output for voltage reference of automotive IC. It provides 250kHz PWM (pulse width modulation) and PFM(pulse frequency modulation) according to load conditions. This device was simulated spectre of IC-design-tools and fabricated Dong-bu Hitec 0.35um BD350BA process.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.208-211
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• 1999

Abstract - Electrical characteristics or asymmetric n-MOSFET's with different source and drain geometry are experimently investigated using test structures having various gate width. Saturation drain current and resistance in linear region are estimated by a simple schematic model, which consists of conventional device having parasitic resistor. A comparison of experimental results of symmetric and asymmetric devices gives the parasitic resistance caused by abnormal device structure. The suggested model shows good agreement with the measured drain current for both forward- and reverse-modes.

• 전력전자학회논문지
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• 제27권1호
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• pp.56-62
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• 2022

In this paper, the effect of pulse width modulation methods on thermal loadings and power losses of single-phase five-level NPC inverters for photovoltaic systems are analyzed. The pulse width modulation methods affect the power losses of the NPC inverters and thus lead to different thermal loadings of NPC inverters. To identify the reliability-critical power device with respect to thermal stress, the thermal loadings of I- and T-type NPC inverters are analyzed by applying the unipolar pulse modulation method. Then, the effect of the discontinuous pulse width modulation method on power losses and thermal loadings of power devices of I- and T-type NPC inverters are analyzed. Finally, the operation of NPC inverters applying the discontinuous pulse modulation method is confirmed by experiments. The results show that the discontinuous pulse modulation method is able to improve the reliability of NPC inverters by reducing thermal loadings of reliability-critical power devices and it is more effective for T-type NPC inverters than I-type NPC inverters.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1407-1410
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• 2007

This work reports on three primary color fluorescent white organic light emitting diode (WOLED) with simple device structure where only a part of the hole transporting layer was doped with dye. The maximum luminance of the device reaches $35000\;cd/m^2$ at a drive voltage below 11V and external quantum efficiency of the device is above 1% in the wide range of luminance from 10 to $35000\;cd/m^2$ and reaches its highest 1.6% at $500\;cd/m^2$. The chromaticity coordinate shift of the device is negligible in this wide range of luminance. The blue shift of emission color with an increase of current density was attributed to the narrowing of recombination zone width with raise of current density.

• Composites Research
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• 제15권4호
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• pp.23-31
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• 2002

시편 게이지 면적($길이{\;}{\times}{\;}폭$)의 이차원 크기효과가 T300/924 $[45/-45/0/90]_3s$ 탄소섬유/에폭시 적층판의 압축거동에 대해 조사하였다. 개조된 압축시험치구(ICSTM)와 좌굴방지장치가 $30mm{\;}{\times}{\;}30mm,{\;}50mm{\;}{\times}{\;}50mm,{\;}70mm{\;}{\times}{\;}70mm,{\;}90mm{\;}{\times}{\;}90mm$의 게이지 길이와 폭을 가진 시편들의 압축시험에 사용하였다. 모든 경우의 파괴들은 시편 게이지 길이 내에서 주로 갑자기 발생하였다. 파괴 후 분석결과는 $0^{\circ}$층의 섬유의 미소좌굴에 의해 파괴를 시작하여 최종파괴를 일으키는 임계파괴기구일 것으로 생각되었다. 이것은 매트릭스 지배적인 파괴를 의미하며, 초기섬유굴곡에 따라 파괴가 지배적으로 시작된다는 것을 말한다 이것은 또한 제작공정과 품질이 압축강도를 결정하는 중요한 역할을 한다고 볼 수 있다. 좌굴방지장치를 장착하고 시험할 때 장치의 볼트 조임 토크에 따라 시편과의 접촉마찰 등에 의해 실제 압축강도 보다 크게 나타나는 결과를 보였다. 좌굴방지장치의 영향을 유한요소법을 이용하여 해석한 결과 실제 압축강도 보다 7% 정도 크게 나타남을 확인하였다. 부가적으로 홀을 갖는 시편들의 압축시험도 수행되었다. 홀에 의한 국부응력집중이 적층판 강도에 지배적 요인이었다. 파괴강도는 홀 크기와 시편 폭이 증가할수록 감소하였으나 탄성응력집중계수로 예측된 값보다는 일반적으로 크게 나타났다. 이것은 사용된 복합재가 이상적인 취성재질이 아니라는 것을 의미하며 홀 주위에서 다소간의 응력이완이 발생한다고 볼 수 있다. X선 검사 사진분석에서 섬유좌굴과 층간분리형태의 손상이 파괴하중의 약 80%에서 홀 가장자리로부터 시작되었고 임계파괴크랙길이인 2-3mm의 불안정한 상태에 도달하기 전까지는 하중 증가와 더불어 안정되게 파괴가 진전되었다(시편의 기하학적 크기에 의존함). 이 손상과 파괴는 선형 cohesive zone 모델로 해석되었다. 노치없는 시편의 압축강도와 평면 파괴인성의 측정된 적층판 변수들을 사용하여 홀의 크기와 시편 폭의 함수로서 홀을 갖는 적층판의 압축강도를 성공적으로 예측하였다.

• 한국신뢰성학회지:신뢰성응용연구
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• 제10권1호
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• pp.65-71
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• 2010

NAND-type SONOS with a separated double-gate FinFET structure (SDF-Fin SONOS) flash memory devices are proposed to reduce the unit cell size of the memory device and increase the memory density in comparison with conventional non volatile memory devices. The proposed memory device consists of a pair of control gates separated along the direction of the Fin width. There are two unique alternative technologies in this study. One is a channel doping method and the other is an oxide thickness variation method, which are used to operate the SDF-Fin SONOS memory device as two-bit. The fabrication processes and the device characteristics are simulated by using technology comuter-adided(TCAD). The simulation results indicate that the charge trap probability depends on the different channel doping concentration and the tunneling oxide thickness. The proposed SDG-Fin SONOS memory devices hold promise for potential application.