• 센서학회지
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• 제28권3호
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• pp.152-156
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• 2019

An ultraviolet (UV) image sensor is an extremely important optoelectronic device used in scientific and medical applications because it can detect images that cannot be obtained using visible or infrared image sensors. Because photodetectors and transistors are based on different materials, conventional UV imaging devices, which have a hybrid-type structure, require additional complex processes such as a backside etching of a GaN epi-wafer and a wafer-to-wafer bonding for the fabrication of the image sensors. In this study, we developed a monolithic GaN UV passive pixel sensor (PPS) by integrating a GaN-based Schottky-barrier type transistor and a GaN UV photodetector on a wafer. Both individual devices show good electrical and photoresponse characteristics, and the fabricated UV PPS was successfully operated under UV irradiation conditions with a high on/off extinction ratio of as high as $10^3$. This integration technique of a single pixel sensor will be a breakthrough for the development of GaN-based optoelectronic integrated circuits.

• 한국진공학회지
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• 제14권2호
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• pp.91-96
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• 2005

양성자 주입과 웨이퍼접합기술을 접목한 ion-cut기술로서 SOI 웨이퍼를 제조하는 기술을 개발하였다. SRIM 전산모사에 의하면 일반 SOI 웨이퍼 (200nm SOI, 400nm BOX) 제조에는 65keV의 양성자주입이 요구된다. 웨이퍼분리를 위한 최적 공정조건을 얻기 위해 조사선량과 열처리조건(온도 및 시간)에 따른 blistering 및 flaking 등의 표면변화를 조사하였다. 실험결과 유효선량범위는 $6\~9times10^{16}H^+/cm^2$이며, 최적 아닐링조건은 $550^{\circ}C$에서 30분 정도로 나타났다. RCA 세정법으로서 친수성표면을 형성하여 웨이퍼 직접접합을 수행하였으며, IR 조사에 의해 무결함접합을 확인하였다 웨이퍼 분리는 예비실험에서 정해진 최적조건에서 이루어졌으며, SOI층의 안정화를 위해 고온열처리($1,100^{\circ}C,\;60$분)를 시행하였다. TEM 측정상 SOI 구조결함은 발견되지 않았으며, BOX(buried oxide)층 상부계면상의 포획전하밀도는 열산화막 계면의 낮은 밀도를 유지함을 확인하였다.

• 정보저장시스템학회:학술대회논문집
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• 정보저장시스템학회 2005년도 추계학술대회 논문집
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• pp.22-25
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• 2005

In this research, a wafar-level transfer method of cantilever array on a conventional CMOS circuit has been developed for high density probe-based data storage. The transferred cantilevers were silicon nitride ($Si_3N_4$) cantilevers integrated with poly silicon heaters and piezoelectric sensors, called thermo-piezoelectric $Si_3N_4$ cantilevers. In this process, we did not use a SOI wafer but a conventional p-type wafer for the fabrication of the thermo-piezoelectric $Si_3N_4$ cantilever arrays. Furthermore, we have developed a very simple transfer process, requiring only one step of cantilever transfer process for the integration of the CMOS wafer and cantilevers. Using this process, we have fabricated a single thermo-piezoelectric $Si_3N_4$ cantilever, and recorded 65nm data bits on a PMMA film and confirmed a charge signal at 5nm of cantilever deflection. And we have successfully applied this method to transfer 34 by 34 thermo-piezoelectric $Si_3N_4$ cantilever arrays on a CMOS wafer. We obtained reading signals from one of the cantilevers.

• 한국신뢰성학회지:신뢰성응용연구
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• 제16권1호
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• pp.26-31
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• 2016

Purpose: The purpose of this study was to investigate the effect of grinding process and thickness on the fracture strength of silicon die used for semiconductor substrate. Method: Silicon wafers with different thickness from $200{\mu}m$ to $50{\mu}m$ were prepared by chemical mechanical polishing (CMP) and dicing before grinding (DBG) process, respectively. Fracture load was measured by point load test for 50 silicon dies per each wafer. Results: Fracture strength at the center area was lower than that at the edge area of the wafer fabricated by DBG process, while random distribution of the fracture strength was observed for the CMPed wafer. Average fracture strength of DBGed specimens was higher than that of the CMPed ones for the same thickness of wafer. Conclusion: DBG process can be more helpful for lowering fracture probability during the semiconductor fabrication process than CMP process.

• 한국전기전자재료학회논문지
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• 제19권10호
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• pp.894-900
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• 2006

This paper reports the fabrication and characterization of $32{\times}32$ thermal cantilever array for nano-scaled memory device applications. The $32{\times}32$ thermal cantilever array with integrated tip heater has been fabricated with micro-electro-mechanical systems(MEMS) technology on silicon on insulator(SOI) wafer using 9 photo masking steps. All of single-level cantilevers(1,024 bits) have a p-n junction diode in order to eliminate any electrical cross-talk between adjacent cantilevers. Nonlinear electrical characteristic of fabricated thermal cantilever shows its own thermal heating mechanism. In addition, n-channel high-voltage MOSFET device is integrated on a wafer for embedding driver circuitry.

• Transactions on Electrical and Electronic Materials
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• 제4권3호
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• pp.29-33
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• 2003

Tri-crystalline silicon wafers have three different orientations and three-grain boundaries. In this paper, tri-crystalline silicon (tri-Si) wafers have been used for the fabrication of buried contact solar cells. The optical and micro-structural properties of these cells after texturing in KOH solution have been investigated and compared with those of cast mult- crystalline silicon (multi-Si) wafers. We employed a cost effective fabrication process and achieved buried contact solar cell (BCSC) energy conversion efficiencies up to $15\%$ whereas the cast multi-Si wafer has efficiency around $14\%$.

• 수산해양교육연구
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• 제19권3호
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• pp.366-372
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• 2007

This paper presents the fabrication techniques of microcooling fins for microelectronics applications. The various types of cooling fins have been fabricated on the surface of a silicon wafer (4inch-N type) by using wet etching technique. The designed micro fins and micro channels are considered as an effective method for cooling microelectronics devices generating high heat flux. Further we extensively investigate the design processes fabricating micro fins and channels which can cool the heat generated from high density electronics devices.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 정기총회 및 추계학술대회 논문집 학회본부
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• pp.192-194
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• 1993

In this paper, a silicon piezoresistive accelerometer of which the cantilevers have uniform thickness is designed and fabricated with SOI wafer. The accelerometer consists of a seismic mass and four cantilevers, and is fabricated mainly by the anisotropic etching method using EPW etchant. The fabrication processes are that of the frontside processes including the etching of the cantilevers and the doubleside alignment holes, the diffusion of the piezoresisters and patterning of the contact windows, and the metal connection process, and that of the backside processes including the etching of the shallow cavity and the seismic mass. Because of the uniformity of thickness, the performance of the accelerometer fabricated with SOI wafer is expected to be better than that of accelerometer fabricated by the time-controlled etching method.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2003년도 춘계학술대회
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• pp.1078-1082
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• 2003

A feasibility study for the fabrication of master replication with nanostructures by Nanoimprint Lithography (NIL) was investigated for application of polymer Photonic Bandgap (PBG) devices used in photonic IC. Large area gratings of $9{\times}15(mm^2)$ with p = 400 nm was successfully embossed on PMMA on silicon wafer and the embossing parameters (temperature, pressure, time) were established. A precise control of $O_2$ plasma Reactive Ion Etching (RIE) process time allowed window opening over the whole area despite the presence of wafer bending. Master replication with aspect ratio 1 was successfully fabricated, but master replication with aspect ratio 3 needs to optimize parameters. All replications were done in a NIL process.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.176-180
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• 2003

Tri-crystalline silicon (Tri-Si) wafers have three different orientations and three grain boundaries. In this paper, tri-Si wafers have been used for the fabrication of buried contact solar cells. The optical and micro-structural properties of these cells after texturing in KOH solution have been investigated and compared with those of cast multi-crystalline silicon (multi-Si) wafers. We employed a cost effective fabrication process and achieved buried contact solar cell (BCSC) energy conversion efficiencies up to 15% whereas the cast multi-Si wafer has efficiency around 14%.