• Journal of the Korean Crystal Growth and Crystal Technology
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• v.10 no.1
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• pp.13-16
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• 2000

Progress in Si crystal and wafer technologies is discussed on single crystal growth, wafer fabrication, epitaxial growth, gettering, 300 mm and SOI. As for bulk crystal growth, the mechanism of grown-in defects (voids) formation, the succes of grown-in defect free crystal growth technology and nitrogen doped crystal are shown. New wafer fabrication technologies such as both-side mirror polishing and etchingless process have been developed. The epitaxial growth of SiGe/Si heterostructure for high speed bipolar device is treated. Gettering technology under low temperature process such as RTP is important, and also it is shown that IG effect for Ni could be predicted using computer simulation of precipitate density and size. The development of 300 mm wafer and SOI has made progress steadily.

• Journal of Korean Institute of Industrial Engineers
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• v.36 no.2
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• pp.125-137
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• 2010

This study focuses on the problem of scheduling wafer lots of several product families in the deposition workstation in a semiconductor wafer fabrication facility. There are multiple identical parallel machines in the deposition workstation, and two types of setups, record-dependent setup and family setup, may be required at the deposition machines. A record-dependent setup is needed to find optimal operational conditions for a wafer lot on a machine, and a family setup is needed between processings of different families. We suggest two-phase heuristic algorithms in which a priority-rule-based scheduling algorithm is used to generate an initial schedule in the first phase and the schedule is improved in the second phase. Results of computational tests on randomly generated test problems show that the suggested algorithms outperform a scheduling method used in a real manufacturing system in terms of the sum of weighted flowtimes of the wafer lots.

• Proceedings of the Korean Society of Propulsion Engineers Conference
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• 2004.03a
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• pp.588-592
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• 2004

This paper presents the preliminary fabrication results of colloid thrusters which can provide thrust of the order of micro to milli-Newtons. MEMS technology has been used for fabrication, and four essential fabrication techniques - deep etching with nested masks, isotropic plasma etching, anisotropic reactive ion etching, and direct fusion wafer bonding - have been newly developed. Among diverse models which have been designed and fabricated, the fabrication results of 4-inch wafer-based colloid thrusters are presented.

• Journal of Korean Institute of Industrial Engineers
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• v.21 no.3
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• pp.357-369
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• 1995

Wafer fabrication process is the most important and critical process in semiconductor manufacturing. The process is very complicated and hard to establish an efficient schedule due to its complexity. Furthermore, several performance indices such as due dates, throughput, cycle time and workstation utilizations are to be considered simultaneously for an efficient schedule, and some of these indices have negative correlations in performances each other. We develop an efficient heuristic scheduling algorithm; Hybrid Input Control Policy and Hybrid Dispatching Rule. Through numerical experiments, it is shown that the proposed Hybrid Scheduling Algorithm gives better performance compared with existing algorithms.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.29 no.11 s.242
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• pp.1463-1471
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• 2005

This paper proposes an agent-based scheduling method fur semiconductor wafer fabrication facilities with hard inter-operation temporal constraints. The scheduling problem is to find the feasible schedules that guarantee both logical and temporal correctness. A proposed multi-agent based architecture is composed of scheduling agents, workcell agents, and machine agents. A scheduling agent computes optimal schedules through bidding mechanisms with a subset or entire set of the workcell agents. A dynamic planning-based approach is adopted for the scheduling mechanism so that the dynamic behaviors such as aperiodic job arrivals and reconfiguration can be taken into consideration.

• Composites Research
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• v.20 no.5
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• pp.49-55
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• 2007

Nanocomposite blade for dicing semiconductor wafer is investigated for micro/nano-device and micro/nano-fabrication. While metal blade has been used for dicing of silicon wafer, polymer composite blades are used for machining of quartz wafer in semiconductor and cellular phone industry in these days. Organic-inorganic material selection is important to provide the blade with machinability, electrical conductivity, strength, ductility and wear resistance. Maintaining constant thickness with micro-dimension during shaping is one of the important technologies fer machining micro/nano fabrication. In this study the fabrication of blade by wet processing of mixing conducting nano ceramic powder, abrasive powder phenol resin and polyimide has been investigated using an experimental approach in which the thickness differential as the primary design criterion. The effect of drying conduction and post pressure are investigated. As a result wet processing techniques reveal that reliable results are achievable with improved dimension tolerance.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.1140-1144
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• 2005

A plastic-based CE (capillary electrophoresis) microchip was fabricated by hot embossing process. A Si mold was made by wet etching process and a PMMA wafer was cut off from 1mm thick PMMA sheet. A micro-channel structure on PMMA substrate was produced by hot embossing process using the Si mold and the PMMA wafer. A vacuum assisted thermal bonding procedure was employed to seal an imprinted PMMA wafer and a blank PMMA wafer. The results of microscopic cross sectional images showed dimensions of channels were well preserved during thermal bonding process. In our procedure, the deformation amount of bonding process was below 1%. The entire fabrication process may be very useful for plastic based microchip systems.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.4
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• pp.273-279
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• 2002

This paper presents a fabrication technology for the integration of single crystal Si microstructures with on-chip circuitry. It is a dissolved wafer technique that combines an electro-chemical etch-stop for the protection of circuitry with an impurity-based etch-stop for the microstructures, both of which are defined in an n-epi layer on a p-type Si wafer. A CMOS op. amp. has been integrated with $p^{++}$ Si accelerometers using this process. It has a gain of 68 dB and an output swing within 0.2 V of its power supplies, unaffected by the wafer dissolution. The accelerometers have $3{\;}\mu\textrm{m}$ thick suspension beams and $15{\;}\mu\textrm{m}$ thick proof masses. The structural and electrical integrity of the fabricated devices demonstrates the success of the fabrication process. A variety of lead transfer methods are shown, and process details are discussed.

• Journal of the Optical Society of Korea
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• v.14 no.2
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• pp.163-169
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• 2010

Novel wafer-level fabrication of a glass ball-lens is realized for optoelectronic applications. A Pyrex wafer is bonded to a silicon wafer and cross-cut into a square-tile pattern, followed by wet-etching of the underlying silicon. Cubes of Pyrex on the undercut silicon are then turned into ball shapes by thermal reflow, and separated from the wafer by further etching of the silicon support. Radial variation and surface roughness are measured to be less than ${\pm}3\;{\mu}m$ and ${\pm}1\;nm$, respectively, for ball diameter of about $500\;{\mu}m$. A surface defect on the ball that is due to the silicon support is shown to be healed by using a silicon-optical-bench. Optical power-relay of the ball lens showed the maximum efficiency of 65% between two single-mode fibers on the silicon-optical-bench.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.32 no.2
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• pp.149-157
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• 2008

During CVD process of semiconductor wafer fabrication, maintaining the uniformity of temperature distribution at wafer top surface is one of the key factors affecting the quality of final products. Effect of contact conductance between wafer and hot plate on predicted temperature of wafer was investigated. The validity of opaque wafer assumption was also examined by comparing the predicted results with Discrete Ordinate solutions accounting for semitransparent radiative characteristics of silicon. As the contact conductance increases predicted wafer temperature increases and the differences between maximum and minimum temperatures within wafer and between wafer and hot plate top surface temperatures decrease. The opaque assumption always overpredicted the wafer temperature compared to semitransparent calculation. The influences of surrounding reactor inner wall temperature and hot plate configuration are then discussed.