• Journal of international Conference on Electrical Machines and Systems
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• 제2권1호
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• pp.97-103
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• 2013

This paper describes the characteristics of Electronic Throttle Controller (ETC) module in BLDC motor without the hall sensor for detecting a rotor position. The proposed ETC control system, which is mainly consisted of a BLDC motor, a throttle plate, a return spring and reduction gear, has a position sensor with an analogue voltage output on the throttle valve instead of BLDC motor for detecting the rotor position. So the additional commutation information is necessarily needed to control the ETC module. For this, the estimation method is applied. In order to improve and obtain the high resolution for the position control, it is generally needed to change the gear ratio of the module or the electrical switching method etc. In this paper, the 3-phase switching between successive commutations is adapted instead of the 2-phase switching that is conventionally used. In addition, the position control with a variable PI gain is applied to improve a dynamic response during a transient period and reduce vibration at a stop in case of matching position reference. The mentioned method can be used to estimate the commutation state and operate the high-precision position control for the ETC module and the high response characteristics. The validity of the proposed method is examined through the experimental results.

• 전자공학회논문지A
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• 제33A권6호
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• pp.99-107
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• 1996

When GPS (global positioning system) is used as synchronous signal in CDMA digital cellular base station system and high speed digital synchronous communication network, antenna cable length is increased, comparing with other GPS application such as positioning or car navigation. In this paper, it is proposed that a type of new GPS antenna system including RF stage for reduction of cable loss in case of long cable.The antenna system with TMPA(truncated-corners microstrip patch antenna) is designed and fabricated because GPS signal has RHCP (right-hand circular polarization), consequently antenna size can be made small size. LNA (low noise amplifier) is designed by using HEMT(high electron mobility transistor)which has lower noise figurae and better AGC characteristics at low voltage than GaAs FET, and we equiped mixer, in GPS antenna unit, which converts from 1575.42MHz to 75.42MHz. As result of comparing between typical system and proposed system when cable length is 60m, 63dB, 55dB and 25dB gain are obtained for RG-316/U, RG-58C/U and RG-213/U, and better characteristics are achieved than typical system as far as cable length is longer.

• 전자공학회논문지D
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• 제36D권5호
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• pp.1-10
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• 1999

저전력으로 동작하고 24리드 SSOP에 실장할 수 있는 2.4 GHz 송수신 MMIC를 1.0㎛ 이온주입 MESFET공정으로 제작하였다. 이MMIC는 송신모드일 때 2.44 GHz에서 3.9 mA의 전류를 소모하였으며 이때 변환이득은 7.5㏈, 출력 IP3는 -3.5 ㏈, 잡음지수는 3.9㏈이었다. 수신모드일 때는 소모전류 2.0mA로 전압검출도 6.5 mV/μW를 나타내었다. 그동안 발표된 다른 MMIC가 우수한 성능을 가지고 있음을 알 수 있었으며 2.4 GHz의 ISM 대역에서 간단한 방식의 무선랜, WLL, RFID 등으로 응용될 것이 기대된다.

• 대한전자공학회논문지TC
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• 제43권3호
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• pp.68-77
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• 2006

본 논문에서는 4.5-5.5GHz 저잡음 증폭기 (low noise amplifiers, LNAs)를 위한 새로운 구조의 검사용 설계(Design-for-Testability, DfT) 회로를 제안한다. 이러한 검사용 설계회로는 고가의 장비를 사용하지 알고도 저잡음 증폭기의 전압 이득, 잡음 지수, 입력 임피던스, 입력 반사 손실 및 출력 신호대 잡음 전력비를 측정한다. 검사용 설계회로는 $0.18{\mu}m$ SiGe 공정을 이용하여 설계되었으며, 입력 임피던스 정합과 직류 출력 전압 측정을 이용한다. 이러한 회로를 이용한 회로 검사 기술은 검사 방법이 간단하고 검사하는데 드는 비용이 저렴하다.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2007년도 추계학술대회 논문집
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• pp.250-254
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• 2007

As photovoltaic(PV) power generation systems become more common, it will be necessary to investigate islanding detection method for PV systems. Islanding of PV systems can cause a variety of problems and must be prevented. However, if the real and reactive powers of the load and PV system are closely matched, islanding detection by passive methods becomes difficult. Also, most active methods lose effectiveness when there are several PV systems feeding the same island. The active frequency drift positive feedback method(AFDPF) enables islanding detection by forcing the frequency of the voltage in the island to drift up or down. In this paper the research for the minimum value of chopping fraction gain applied digital phase-locked-loop (DPLL) to AFDPF considering output power quality and islanding prevention performance are performed by simulation and experiment according to IEEE Std 929-2000 islanding test.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권2호
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• pp.106-113
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• 2006

Electrical properties of $Si_{0.88}Ge_{0.12}(C)$ p-MOSFETs have been exploited in an effort to investigate $Si_{0.88}Ge_{0.12}(C)$ channel structures designed especially to suppress diffusion of dopants during epitaxial growth and subsequent fabrication processes. The incorporation of 0.1 percent of carbon in $Si_{0.88}Ge_{0.12}$ channel layer could accomodate stress due to lattice mismatch and adjust bandgap energy slightly, but resulted in deteriorated current-voltage properties in a broad range of operation conditions with depressed gain, high subthreshold current level and many weak breakdown electric field in gateoxide. $Si_{0.88}Ge_{0.12}(C)$ channel structures with boron delta-doping represented increased conductance and feasible use of modulation doped device of $Si_{0.88}Ge_{0.12}(C)$ heterostructures.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권2호
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• pp.85-90
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• 2009

This paper presents a single supply PLC SoC ASIC with a built-in analog Front-end circuit. To achieve the low power consumption along with low cost, this PLC SoC employs fully CMOS Analog Front End (AFE) and several LDO regulators (LDOs) to provide the internal power for Logic Core, DAC and Input/output Pad driver. The receiver part of the AFE consists of Pre-amplifier, Gain Amplifier and 1 bit Comparator. The transmitter part of the AFE consists of 10 bit Digital Analog Converter and Line Driver. This SoC is implemented with 0.18 ${\mu}m$ 1 Poly 5 Metal CMOS Process. The single supply voltage is 3.3 V and the internal powers are provided using LDOs. The total power consumption is below 30 mA at stand-by mode to meet the Eco-Design requirement. The die size is 3.2 $\times$ 2.8 $mm^{2}$.

• 전자공학회논문지 IE
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• 제49권1호
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• pp.1-6
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• 2012

본 논문에서는 시간-디지털 변환기의 성능 개선을 위하여, 높은 해상도의 2단 시간-디지털 변환기(TDC)를 설계하였다. TDC 중간에 2단 버니어 시간 증폭기(2-S VTA)를 사용하여 2단 구조를 갖도록 하였다. 2단 버니어 시간 증폭기는 기존의 시간 증폭기에 비해 이득이 64 이상으로 매우 크기 때문에 전체 2단 TDC의 해상도를 높인다. TDC는 버니어 구조를 사용하였기 때문에 고급 공정에 제한받지 않고, 높은 해상도를 얻을 수 있다. 제안하는 2단 TDC는 $0.18{\mu}m$ CMOS 공정으로 설계하였고, 전원 전압은 1.8V로 모의실험 하였다. 전체 입력 범위는 512ps이고 전체 해상도는 0.125ps이다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.781-792
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• 2016

This paper presents a new approach to enhance the data retention of logic-compatible embedded DRAMs. The memory bit-cell in this work consists of two logic transistors implemented in generic triple-well CMOS process. The key idea is to use the parasitic junction capacitance built between the common cell-body and the data storage node. For each write access, a voltage transition on the cell-body couples up the data storage levels. This technique enhances the data retention and the read performance without using additional cell devices. The technique also provides much strong immunity from the write disturbance in the nature. Measurement results from a 64-kbit eDRAM test chip implemented in a 130 nm logic CMOS technology demonstrate the effectiveness of the proposed circuit technique. The refresh period for 99.9% bit yield measures $600{\mu}s$ at 1.1 V and $85^{\circ}C$, enhancing by % over the conventional design approach.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.825-831
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• 2016

In this paper, a transimpedance amplifier based on a new DC offset cancellation (DCOC) method is proposed for WCDMA/LTE applications. The proposed method applies a sample and hold mechanism to the conventional DCOC method with a DC feedback loop. It prevents the removal of information around the DC, so it avoids signal-to-noise ratio degradation. It also reduces area and power consumption. It was designed in a $0.13{\mu}m$ deep n-well CMOS technology and drew a maximum current of 1.58 mA from a 1.2 V supply voltage. It showed a transimpedance gain of $80dB{\Omega}$, an input-referred noise current lower than 0.9 pA/${\surd}$Hz, an out-of-band input-referred 3rd-order intercept point more than 9.5 dBm, and an output DC offset lower than 10 mV. Its area is $0.46mm{\times}0.48mm$.