Browse > Article

A Study on the Performance Improvement of a Time-to-Digital Converter  

Ahn, Tae-Won (Dongyang Mirae University)
Lee, Jong-Suk (Soongsil University)
Moon, Yong (Soongsil University)
Publication Information
전자공학회논문지 IE / v.49, no.1, 2012 , pp. 1-6 More about this Journal
Abstract
For the performance improvement of a time-to-digital converter(TDC), a 2-stage high resolution TDC has been designed by using a 2-stage vernier time amplifier(2-S VTA). The two stage vernier time amplifier which has a gain over 64 of the resolution can enhance the resolution of the whole two stage TDC. Because of using a vernier TDC, the structure is not limited to advanced processes for achieving high resolution. The proposed TDC has been designed in a $0.18{\mu}m$ CMOS process and simulated with a 1.8V supply voltage. The entire input range is 512ps, and the full resolution 0.125ps.
Keywords
TDC;
Citations & Related Records
연도 인용수 순위
  • Reference
1 김용우, 안태원, 문용, "디지털 PLL을 위한 높은 해상도를 갖는 시간-디지털 변환기의 연구," 대한전자공학회 2008년 하계종합학술대회, pp. 587-588
2 안태원, 이종석, 문용, "인버터 체인을 이용한 고속 2단 시간-디지털 변환기," 대한전자공학회 2011년 하계종합학술대회, pp. 1465-1467
3 A. M. Abas et al., "Time difference amplifier," Electron. Lett., vol. 38, no. 23, pp. 1437-1438, Nov. 2002   DOI   ScienceOn
4 M. Lee and Asad A. Abidi, "A 9b, 1.25ps Resolution Coarse - Fine Time-to-Digital Converter in 90nm CMOS that Amplifies a Time Residue," IEEE JSSC, vol.43, no.4, pp.168-169, June 2007
5 Seon-Kyoo Lee, Young-Hun Seo, Yunjae Suh, Hong-June Park, Jae-Yoon Sim, "A 1GHz ADPLL with a 1.25ps Minimum-Resolution Sub-Exponent TDC in $0.18{\mu}m$ CMOS," IEEE ISSCC, pp.482-483, Feb. 2010
6 Kuo-Hsing Cheng, Chang-Chien Hu, Jen-Chieh Liu, Hong-Yi Huang, "A Time-to-Digital Converter Using Multi-Phase-Sampling and Time Amplifier for All Digital Phase-Locked Loop," IEEE DDECS, pp.285-288, Apr. 2010