• Journal of Power Electronics
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• 제5권4호
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• pp.312-318
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• 2005

This paper presents a compensator for reduction of the reactive lateral current in multiple autonomously controlled uninterruptible power supplies (UPS) connected in parallel. This compensator acts directly on the control equation for voltage amplitude and it provides an improved current distribution especially in the case of parallel connection of UPSs with different output power ratings. Observations show that the original control equation for output voltage amplitude is efficient for voltage regulation but it causes great variation of voltage levels. A compensator with the same structure is added to counterbalance the variation caused by the original control equation. Simulations show promising results with the employment of the proposed compensator. Our simulations are confirmed by experimental results using three UPSs with different output ratings and voltage limiters ($1\%$) connected in parallel under various conditions.

• 대한기계학회논문집A
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• 제28권1호
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• pp.1-10
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• 2004

This paper presents a navigation garde capacitive microaccelerometer, whose low-noise high-resolution detection capability is achieved by a new electrode design based on a high-amplitude anti-phase sense voltage. We reduce the mechanical noise of the microaccelerometer to the level of 5.5$\mu\textrm{g}$/(equation omitted) by increasing the proof-mass based on deep RIE process of an SOI wafer. We reduce the electrical noise as low as 0.6$\mu\textrm{g}$/(equation omitted) by using an anti-phase high-amplitude square-wave sense voltage of 19V. The nonlinearity problem caused by the high-amplitude sense voltage is solved by a new electrode design of branched finger type. Combined use of the branched finger electrode and high-amplitude sense voltage generates self force-balancing effects, resulting in an 140％ increase of the bandwidth from 726㎐ to 1,734㎐. For a fixed sense voltage of 10V, the total noise is measured as 2.6$\mu\textrm{g}$/(equation omitted) at the air pressure of 3.9torr, which is the 51％ of the total noise of 5.1$\mu\textrm{g}$/(equation omitted) at the atmospheric pressure. From the excitation test using 1g, 10㎐ sinusoidal acceleration, the signal-to-noise ratio of the fabricated microaccelerometer is measured as 105㏈, which is equivalent to the noise level of 5.7$\mu\textrm{g}$/(equation omitted). The sensitivity and linearity of the branched finger capacitive microaccelerometer are measured as 0.638V/g and 0.044％, respectively.

• 한국전기전자재료학회논문지
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• 제16권10호
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• pp.931-937
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• 2003

The principle of the superconducting vortex flow transistor (SVFT) is based on control of the Abrikosov vortex flowing along a channel. The induced voltage is controlled by a bias current and a control current, instead of external magnetic field. The device is composed of parallel weak links with a nearby current control line. We explained the process to get an I-V characteristic equation and described the method to induce the external and internal magnetic field by the Biot-Savarts law in this paper. The equation can be used to predict the I-V curves for fabricated device. From the equation we demonstrated that the current-voltage characteristics were changed with input parameters. I-V characteristics were simulated to analyze a SVFT with multi-channel by a computer program.

• 대한전기학회논문지:시스템및제어부문D
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• 제50권2호
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• pp.93-99
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• 2001

A new type geometric and mathematical network reduction model is introduced. Large-scale network is analyzed with analytic approach. The graph has many nodes, branches and loops. Circuit equation are obtained from these elements and connection rule. In this paper, the analytic relation between voltage source has a mutual different graphic property. Node-reduction procedure is achieved with this circuit property. Consequently voltage source value is included into the adjacent node-analyzing equation. A resultant model equations are reduced as much as voltage source number. Matrix rank is (n-1-k), where n, k is node and voltage source number. The reduction procedure is described and verified with geometric principle and circuit theory. Matrix type circuit equation can be composed with this technique. The last results shall be calculated by using computer.

• 전기전자학회논문지
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• 제22권3호
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• pp.716-722
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• 2018

This paper presents a voltage angle control strategy for surface permanent magnet synchronous motor (SPMSM) drives used in low-cost applications, wherein a current vector control is not employed. In the proposed method, the current vector control scheme, which requires high precision phase-current sensing units and a fast calculation capability of a motor drive controller, is replaced with the voltage angle controller. The proposed voltage angle controller calculates a d-axis voltage command to make the d-axis current zero by using a simple equation obtained from the voltage equation of SPMSM. The proposed method shows performance similar to the current vector controlled SPMSM drive during steady-states and its structure is very simple and thus it can be easily implemented with a low-cost microcontroller. The effectiveness of the proposed method is verified through simulations and experiments.

• 한국정보통신학회논문지
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• 제17권2호
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• pp.372-377
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• 2013

DGMOSFET의 항복전압에 대하여 고찰하였으며 이를 위하여 포아송방정식의 분석학적 해 및 Fulop의 항복전압 조건을 사용하였다. DGMOSFET는 게이트단자의 전류제어능력 향상으로 단채널 효과를 감소시킬 수 있다는 장점이 있다. 그러나 단채널에서 나타나는 항복전압의 감소는 피할 수 없으므로 이에 대한 연구가 필요하다. 포아송방정식을 풀 때 사용하는 전하분포함수에 가우시안 함수를 적용함으로써 보다 실험값에 가깝게 해석하였으며 이때 이중게이트 MOSFET의 소자크기에 따라 항복전압의 변화를 관찰하였다. 본 연구의 전위모델에 대한 타당성은 이미 기존에 발표된 논문에서 입증하였으며 본 연구에서는 이 모델을 이용하여 항복전압을 분석할 것이다. DGMOSFET의 항복전압을 관찰한 결과, 채널길이가 감소할수록 그리고 도핑농도가 증가할수록 항복전압이 감소하는 것으로 나타났다. 또한 게이트산화막 두께 및 채널두께에 따라서 항복전압의 변화가 관찰되었다.

• Journal of information and communication convergence engineering
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• 제7권1호
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• pp.57-61
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• 2009

This paper has presented the subthreshold current model of FinFET using the potential variation in the doped channel based on the analytical solution of three dimensional Poisson's equation. The model has been verified by the comparison with the data from 3D numerical device simulator. The variation of subthreshold current with front and back gate bias has been studied. The variation of subthreshold swing and threshold voltage with front and back gate bias has been investigated.

• ETRI Journal
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• 제31권1호
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• pp.42-50
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• 2009

A new method for simulating voltage and current distributions in transmission lines is described. It gives the time domain solution of the terminal voltage and current as well as their line distributions. This is achieved by treating voltage and current distributions as distributed state variables (DSVs) and turning the transmission line equation into an ordinary differential equation. Thus the transmission line is treated like other lumped dynamic components, such as capacitors. Using backward differentiation formulae for time discretization, the DSV transmission line component is converted to a simple time domain companion model, from which its local truncation error can be derived. As the voltage and current distributions get more complicated with time, a new piecewise exponential with controllable accuracy is invented. A segmentation algorithm is also devised so that the line is dynamically bisected to guarantee that the total piecewise exponential error is a small fraction of the local truncation error. Using this approach, the user can see the line voltage and current at any point and time freely without explicitly segmenting the line before starting the simulation.

• 비파괴검사학회지
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• 제20권2호
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• pp.110-115
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• 2000

전기-기계 상호관계식을 사용하여 시편에서의 산란파를 탐촉자의 전기 신호로 변환시키는 방법을 다루었다. 산란파에 의한 탐촉자의 전기 신호는 입사파와 산란파의 변위, 응력 관계식의 적분으로 표시되었다. 적분 표면은 산란자를 포함하는 닫힌 표면이며 입사파와 산란파의 변위, 응력도 이 표면 좌표에서의 값을 사용한다. 파동해석 결과에서 구한 산란된 파동으로부터 초음파 현미경의 탐촉자 전기 신호를 구했으며 계산 결과를 실험 결과와 비교하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권3호
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• pp.173-181
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• 2005

A new two dimensional (2-D) model for the potential distribution of fully depleted short-channel ion-implanted silicon MESFET's has been presented in this paper. The solution of the 2-D Poisson's equation has been considered as the superposition of the solutions of 1-D Poisson's equation in the lateral direction and the 2-D homogeneous Laplace equation with suitable boundary conditions. The minimum bottom potential at the interface of the depletion region due to the metal-semiconductor junction at the Schottky gate and depletion region due to the substrate-channel junction has been used to investigate the drain-induced barrier lowering (DIBL) and its effects on the threshold voltage of the device. Numerical results have been presented for the potential distribution and threshold voltage for different parameters such as the channel length, drain-source voltage, and implanted-dose and silicon film thickness.