• Journal of the Microelectronics and Packaging Society
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• v.14 no.3
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• pp.65-71
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• 2007

For chip-stack package applications, Cu filling characteristics into trench vias of $75{\sim}10\;{\mu}m$ width and 3 mm length were investigated with variations of the electroplating current density and the speed of a rotating disc electrode (RDE). Cu filling characteristics into trench vias were improved with increasing the RDE speed. There was a Nernst relationship between half width of trench vias of Cu filling ratio higher than 95% and the minimum RDE speed, and the half width of trenches with 95% Cu filling ratio was linearly proportional to the reciprocal of root of the minimum RED speed.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.4
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• pp.99-104
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• 2015

The requirement for success of via filling is its ability to fill via holes completely without producing voids or seams. Defect free via filling was obtained by optimizing plating conditions such as current mode, current density and additives. However, byproducts stemming from the breakdown of these organic additives reduce the lifetime of the devices and plating solutions. In this study, the relationship between JGB and current density on the copper via filling was investigated without the addition of other additives to minimize the contamination of copper via. AR 4 with $15{\mu}m$ diameter via were used for this study. The pulse current was used for the electroplating of copper and the current densities were varied from 10 to $20mA/cm^2$ and the concentrations of JGB were varied from 0 to 25 ppm. The map for the JGB concentration and current density was developed. And the optimum conditions for the AR 4 via filling with $15{\mu}m$ diameter were obtained.

• Korean Journal of Metals and Materials
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• v.49 no.5
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• pp.388-394
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• 2011

High speed copper filling into TSV (through-silicon-via) for three dimensional stacking of Si chips was investigated. For this study, a tapered via was prepared on a Si wafer by the DRIE (deep reactive ion etching) process. The via had a diameter of 37${\mu}m$ at the via opening, and 32${\mu}m$ at the via bottom, respectively and a depth of 70${\mu}m$. $SiO_2$, Ti, and Au layers were coated as functional layers on the via wall. In order to increase the filling ratio of Cu into the via, a PPR (periodic pulse reverse) wave current was applied to the Si chip during electroplating, and a PR (pulse reverse) wave current was applied for comparison. After Cu filling, the cross sections of the vias was observed by FE-SEM (field emission scanning electron microscopy). The experimental results show that the tapered via was filled to 100% at -5.85 mA/$cm^2$ for 60 min of plating by PPR wave current. The filling ratio into the tapered via by the PPR current was 2.5 times higher than that of a straight via by PR current. The tapered via by the PPR electroplating process was confirmed to be effective to fill the TSV in a short time.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.11a
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• pp.20-20
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• 2004

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.57-63
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• 2006

For chip-stack package applications, Cu filling characteristics into trench vias of $75{\sim}10\;{\mu}m$ width and 3 mm length were investigated with variations of electroplating current density and current mode. At $1.25mA/cm^{2}$ of DC mode, Cu filling ratio higher than 95% was obtained for trench vias of $75{\sim}35{\mu}m$ width. When electroplated at DC $2.5mA/cm^{2}$, Cu filling ratios became inferior to those processed at DC $1.25mA/cm^{2}$. Pulse current mode exhibited Cu filling characteristics superior to DC current mode.

• Korean Journal of Materials Research
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• v.23 no.10
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• pp.550-554
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• 2013

As continued scaling becomes increasingly difficult, 3D integration has emerged as a viable solution to achieve higher bandwidths and good power efficiency. 3D integration can be defined as a technology involving the stacking of multiple processed wafers containing integrated circuits on top of each other with vertical interconnects between the wafers. This type of 3D structure can improve performance levels, enable the integration of devices with incompatible process flows, and reduce form factors. Through silicon vias (TSVs), which directly connect stacked structures die-to-die, are an enabling technology for future 3D integrated systems. TSVs filled with copper using an electro-plating method are investigated in this study. DC and pulses are used as a current source for the electro-plating process as a means of via filling. A TiN barrier and Ru seed layers are deposited by plasma-enhanced atomic layer deposition (PEALD) with thicknesses of 10 and 30 nm, respectively. All samples electroplated by the DC current showed defects, even with additives. However, the samples electroplated by the pulse current showed defect-free super-filled via structures. The optimized condition for defect-free bottom-up super-filling was established by adjusting the additive concentrations in the basic plating solution of copper sulfate. The optimized concentrations of JGB and SPS were found to be 10 and 20 ppm, respectively.

• Journal of Welding and Joining
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• v.32 no.3
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• pp.11-18
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• 2014

TSV(through silicon via) filling technology is making a hole in Si wafer and electrically connecting technique between front and back of Si die by filling with conductive metal. This technology allows that a three-dimensionally connected Si die can make without a large number of wire-bonding. These TSV technologies require various engineering skills such as forming a via hole, forming a functional thin film, filling a conductive metal, polishing a wafer, chip stacking and TSV reliability analysis. This paper addresses the TSV filling using Cu electrodeposition. The impact of plating conditions with additives and current density on electrodeposition will be considered. There are additives such as accelerator, inhibitor, leveler, etc. suitably controlling the amount of the additive is important. Also, in order to fill conductive material in whole TSV hole, current wave forms such as PR(pulse reverse), PPR(periodic pulse reverse) are used. This study about semiconductor packaging will be able to contribute to the commercialization of 3D TSV technology.

• Korean Chemical Engineering Research
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• v.54 no.6
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• pp.723-733
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• 2016

Intensive researches have been focused on the 3-dimensional packaging technology using through silicon via (TSV) to overcome the limitation in Cu interconnection scaling. Void-free filling of TSV by the Cu electrodeposition is required for the fabrication of reliable electronic devices. It is generally known that sufficient inhibition on the top and the sidewall of TSV, accompanying the selective Cu deposition on the bottom, enables the void-free bottom-up filling. Organic additives contained in the electrolyte locally determine the deposition rate of Cu inside the TSV. Investigation on the additive chemistry is essential for understanding the filling mechanisms of TSV based on the effects of additives in the Cu electrodeposition process. In this review, we introduce various filling mechanisms suggested by analyzing the additives effect, research on the three-additive system containing new levelers synthesized to increase efficiency of the filling process, and methods to improve the filling performance by modifying the functional groups of the additives or deposition mode.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2009.10a
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• pp.171-172
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• 2009

TSV(through via silicon)를 이용한 Via의 Cu 충전에서 Seed 층의 역할은 전류의 흐름을 가능하게 하는 중요한 역할을 하고 있다. Via에 각각 Ti/Au, Ti/Cu를 증착한 후 Ti/Cu가 Ti/Au를 대체 할 수 있는지를 알아보기 위해 먼저 실리콘 웨이퍼에 via를 형성하고, 형성된 via에 기능성 박막층으로 절연층(SiO2) 및 시드층을 형성하였다. 전해도금을 이용하여 Cu를 충전한 결과 Ti/Au 및 Ti/Cu를 증착한 두 시편 모두 via와 seed층 접합면에 박리 등의 결함이 없었고, via 내부 또한 void나 seam 등이 관찰되지 않고 우수하게 충전된 것을 확인할 수 있었다.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2011.06a
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• pp.743-744
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• 2011